I am attempting to route a HyperRAM BGA chip with a HyperBus OctoSPI interface to an STM32 MCU. This is on a 2 layer board. After much consideration, I have determined that the best placement of the chip was directly below the MCU, on the opposite side of the board.

Although this allows for relatively short signal lengths, it neccessitates the use of vias for every data and clock connection. I understand that this is not a good idea for high speed signals, and wonder if the following routing will be acceptable for signals at 166MHz maximum? Especially of concern is the clock signal (OCTOSPI1_CLK), which crosses over 3 data lines. I have tried to route the clock as far away from data lines and as straight as possible, but it does not appear possible to prevent crossovers while keeping the track at a reasonable length with the current placement.


Blue traces are on the bottom layer (which the HyperRAM chip is on), and red traces are on the front layer (which the MCU is on). Could there be any placement allowing for higher signal quality?


Following the advice of the first answer, I have attempted to reroute the BGA HyperRAM chip on the same side of the board as the MCU, and use a 4-layer PCB.

alternate routing

The PCB layout is as follows:

  1. (Top) GND fill, MCU & HyperRAM
  2. (In1) GND fill
  3. (In2) 3V3 fill, crossed-over connections routed in this layer
  4. (Bottom): GND fill

A layer change was necessary for one of the data lines. I have also added a guard trace near to the clock line, and followed routing practices as suggested by the Infineon layout guide. I'm hoping that this is a significant improvement over the first one?


1 Answer 1


It just might. But it's really hard to predict; high-speed data lines crossing with no ground layer in between is always a bit meh, and adding parallel vias is worse. (You have no ground plane with which the signal lines form a waveguide that actually carries the signal power, meaning that signal propagates "somewhere" in the substrate and the air surrounding the traces. Now, through that you enhance the amount of energy coupled out of the trace, and you enhance the susceptibility to such energy. Add vias that are close to each other, and you build something that looks more like a resonator experiment than properly laid out signal lines. Still, this is all relatively small compared to a wavelength, so, hm.) I would not count on it; this really breaks all the rules of thumb, and you'd want to do an EM simulation on it before committing to a larger production run.

Your problem here is the two-layer board, which the HyperRAM doesn't seem to be designed for.

For mass-production, requiring both-side fine-pitch soldering will probably drive the price up more than going for a 4-layer PCB (in fact, Chinese PCB houses make these pretty cheap these days), and for manual / small series production, the additional cost of 4 layers will be rapidly outshined by the additional effort you have, plus the higher risk that the first batch of boards simply doesn't work as intended.

Also, you avoided 3 vias for power by adding 10 vias for high-speed signals. That's a bad trade.

The chip pin configuration was designed for putting the chip on the same side of the board (in the picture, along the left "long" side), when you look at it, you get zero trace crossings when you connect, from top to bottom, NCS, CLK, DQS, I00…I07, in that order.


Go for 4 layers, and put the memory on the same side of the board as the MCU. There is a crossing-free trace order you can use, so don't use a single signal trace via if your MCU allows for a compatible pin ordering.

  • \$\begingroup\$ Thanks for the extremely well-written answer! I have attempted to route the traces with the chip in the suggested orientation, however it doesn't appear possible to route all traces without overlaps. Namely, the CLK and DQS pins are obstructed by other pins: screenshot for reference. \$\endgroup\$ Aug 20, 2023 at 14:20
  • \$\begingroup\$ infineon.com/dgdl/… page 5 for reference; most memory controllers use a pinout that enables this. If your STM chip doesn't, hm, is swapping some pins an option? If the size of the memory is a power of 2, then it doesn't matter how you permute the address bits, and since a permutation in data bits doesn't matter anyway (they're read as they were written!), that'd solve the problem. \$\endgroup\$ Aug 20, 2023 at 15:34
  • \$\begingroup\$ (that might make using built-in controllers harder, because commands might need to be translated…) \$\endgroup\$ Aug 20, 2023 at 15:39
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    \$\begingroup\$ To my knowledge, it is not feasible to swap data or address pins as the HyperBus protocol uses commands, managed by the controller, to initiate data transfer (e.g. burst read/write). It doesn't appear possible to route without any crossings, but I have found a routing which only requires a single via in data lines (prioritising them as recommended by the Infineon document). \$\endgroup\$ Aug 21, 2023 at 0:02
  • \$\begingroup\$ I have made an edit to the OP with a new layout incorporating your suggestions. Would appreciate your comments on it! \$\endgroup\$ Aug 22, 2023 at 12:50

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