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I'm attempting to test a parameter of an IC to the specifications listed in the data sheet. The data sheet describes the following load circuitry for the output:

Switching  time test circuit

The data sheet notes that CL be 50pF minimum, and that the diodes be 1N3064 or equivalent.

The device I'm testing has six outputs that need to be tested for an implied total of 42 discretes that I'd need on my PCB. I suppose I could use a header/jumper system to change which output of the IC is connected to a single load circuit on the board but that would require the load to be not that close to the output, sort of on it's own "branch" of the trace which I believe would be detrimental to the timing measurements I'm trying to make.

I suppose I have a few questions, any of which could help me here:

  • When the data sheet says "1N3064 or equivalent," what parameters of the 1N3064 are important? The 1N3064 is an axial device and I will probably have to find a surface-mount equivalent.

  • Is there something magical about this configuration that I'm missing? For example, that four diodes actually being equivalent to some other type of component that would be easier to place on a board?

  • Would switching a single load with jumpers make my life easier or more difficult?

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  • \$\begingroup\$ What kind of rise and fall times are you trying to measure? To get an idea whether headers and jumpers are a problem or not. \$\endgroup\$ – The Photon May 1 '13 at 20:35
  • \$\begingroup\$ Data sheet specifies TPHL=3ns to 99ns, TPLH=3ns to 140ns. \$\endgroup\$ – TheNoonMoose May 1 '13 at 20:39
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    \$\begingroup\$ Only a guess: the circuit simulates several inputs of the same logic family in parallel. If you could get an 8-channel buffer or something from that family, you might be able to hook up all of its inputs in parallel to achieve a similar load. For times above 10 or 20 ns you should be just fine using headers and jumpers to move the load around. You probably don't need to worry about the 3 ns end of the spec --- that would only apply in a minimum capacitive load situation. \$\endgroup\$ – The Photon May 1 '13 at 20:46
  • \$\begingroup\$ It is in fact equivalent to single TTL input. TTL family has open emitter inputs. That Base-emitter junction is horizontal diode in picture. 3 diodes in series are base-collector of NPN transistor followed by 2 base-emitter junctions cascaded. As The Phantom noted, you can use simple TTL buffer input as load. \$\endgroup\$ – mj6174 May 1 '13 at 21:34
  • \$\begingroup\$ @Mandar, sounds like an answer. \$\endgroup\$ – The Photon May 1 '13 at 21:35
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The load is in fact equivalent to single TTL input. TTL family has open emitter inputs. That Base-emitter junction is horizontal diode in picture. 3 diodes in series are base-collector of NPN transistor followed by 2 base-emitter junctions cascaded. As The Phantom noted, you can use simple TTL buffer input as load.

You can see typical internal circuit for TTL gate on page 9.

ftp://apollo.ssl.berkeley.edu/pub/cinema/04.%20Science/TTL%20Cookbook_0672210355.pdf

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protected by W5VO May 1 '13 at 21:13

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