This is my first attempt at designing a discrete digital circuit.

Basically I'm looking to count the number of times a button is pressed. Each button press will trigger a new output. And the final button press will trigger a reset.

Basically I'm trying to make a 5 bit register where each bit will be a 1.

I have 74HC373s on hand. From all the reading I've done it seems like this part should be usable as a shift register. I just can't get it to simulate properly.

If I set the enable high using the push button, it will set all bits to 1 on the first click. If I clock the enable pin, it seems to be resetting every time the pin goes low which doesn't really make sense to me for a latch.

Does anybody have any experience simulating this part in Multisim 14?

Does this sound like typical behavior, or should I just go ahead and develop the circuit in solder instead of simulating?

  • \$\begingroup\$ Apropos input: how do you connect inputs&outputs? For salutations and expressing appreciation, please see Expected Behaviour on chitchat. \$\endgroup\$
    – greybeard
    Aug 24, 2023 at 5:07

2 Answers 2


The 74HC373 is a transparent latch. This means, as long as LE is high, the internal latches follow their inputs.

Assuming that you use this circuit or similar: enter image description here

If Enable is high, the value at Shift In will be propagated through all eight latches. So your observation is correct, this is the expected behaviour.

To solve the issue, replace the 74HC373 with a 74HC374. This uses edge-triggered flip flops, and you will get what you want. The pinning is identical:

enter image description here

  • \$\begingroup\$ So for the 373 it is normal for it to reset all outputs once the enable pin goes low? The datasheet wasn't terribly clear about that so I made the mistake of thinking it was basically the same behavior as the 374 but could be triggered by the entire pulse, not just the edge. Clarified now, thanks. \$\endgroup\$ Aug 24, 2023 at 7:56
  • \$\begingroup\$ No, the outputs become low, if the inputs go low even in the latest moment before the enable signals becomes inactive. See the data sheet for the hold time. Unfortunately you show no timing diagrams in your question. \$\endgroup\$ Aug 24, 2023 at 8:17

You can do a shift register using "transparent latches":

You need clock signals that don't overlap (guarantee set-up and hold times between interconnected latches), each pair of latches constituting a "dual-edge triggered master-slave flip-flop".

Or use latches with alternating enable active levels (¬S¬R&SR/NAND&NOR) latches: shift register/Johnson counter at falstad.com (inverter not strictly necessary for Johnson counter).

The '373 having a single enable, a single '373 won't do, a single '75/'375 still needs a "complementary element" ('87, anyone?).

  • \$\begingroup\$ So by "not overlap", would a 50 percent duty cycle be considered overlapping? Because that dirty duty cycle wipes the latch when it goes low. \$\endgroup\$ Aug 25, 2023 at 0:26
  • \$\begingroup\$ I see no direct connection between duty cycle and overlap. \$\endgroup\$
    – greybeard
    Aug 28, 2023 at 6:22

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