I'm writing some verilog and simulating it using modelsim. I have a block that looks like this:
if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1) begin cam_we <= 1; cam_wr_addr <= wr_addr; cam_din <= wr_cmp_data ; cam_data_mask <= wr_cmp_dmask; wr_ack <= 1; lut_wr_data <= wr_data; end
lookup_latched is in high impedence.
cam_match_found_d1 are both in don't care states.
It seems to me like the statement should just ignore those signals.
The one issue I noticed was that the signals were being bitwise anded instead of logically anded (I didn't write the code). Will this have an affect on the result? (I imagine it will)