I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock.

The data are read from an SDRAM and are fed into the VGA output.
To do that I use the intel DCFIFO IP and PLL IP. The PLL is fed by a 50 MHz clock.
To test the setup I write a sequence from 0 to 4095 into the ram and read it out again (observing it via Signal Tap). When I set the rdclock to 100, 50 or 25 MHz everything works fine but as soon as I set it to 25.175 MHz (requested settings) or to be precise 25.170068 actual settings it goes south.

The FIFO begins to stumble like [2, 3, 10, 4, 6, 7]. I tried to set the FIFO to "best metastability protection" using different counts of sync stages without any effect. Then I tried to combine that settings with "Asynchronous clear" and "add circuit to synchronize 'aclr' with 'wrclck'" and "add circuit to synchronize 'aclr' with 'rdclk'" it get's much better but after a few dozen cycles it starts again.
It's like [1, 2, 3, 4, 5, 6, ..., 100, 2542, 2156, 200, 201, 202].

It's obviously a problem with the .175 value but I don't know how to solve it.
The other question is: why does the aclr settings make it better? I read about it but have to admit that I didn't fully understand it yet.

After getting some questions in the comments I'll add some context:

  1. I'm using a DE10-lite board it uses a MAX 10 10M50DAF484C7G FPGA.
  2. Yes, the FIFO doesn't care about the clock but since it only crashes when using the .175 MHz value I suspected some coincidence.
  3. The FIFO is 256 words deep with 16 bit words. It crashes around after value 256. Now you could say - aah you may have disabled overflow protection and it's overflowing, but I didn't and it gets read at the same time so even if it's an overflow issue I would expect it to happen a bit later.
  4. I can't supply a simulation yet, but nothing but the FIFO (and the VGA controller) is connected to the 25 clock so I can't imagine where a frequency change could influence the rest of the design.
  5. I realized that the FIFO output stablizes when I connect the 25.175 MHz clock to the rdclock but use the 96MHz clock as Signal Tap sampling clock. Thus the question arises if this is an issue with my design or with signal tap.

Update 2: (not true anymore, pls see 2.1) After adding an actual VGA display to my setup I realized that the system works correctly and Signal Tap is just "haluscinating" the stumbling FIFO.
I also want to stress the point that the strange things start to happen when Signal Tap clock and FIFO clock are the same! Signal Tap generates a stable output when using 96 or 100MHz as ST clock and 25.175 as FIFO clock but starts to misbehave when both are using 25.175.

Update 2.1
Due to the added VGA display I made another observation:
Signal Tap is not lying at all. When I set the VGA clock as Signal Tap clock the whole system crashes. Either I am misunderstanding some basic point or Signal Tap influences my design in some way. I added two screenshots to show what I understand by signal tap clock. I always thought that this would only affect the sample rate of signal tap. enter image description here enter image description here

  • \$\begingroup\$ What chip are you using here? Is this an FPGA of some description? Which one specifically? \$\endgroup\$
    – Hearth
    Aug 24 at 19:48
  • 3
    \$\begingroup\$ The DCFIFO core doesn't care about the clock frequency - It doesn't know the difference between 25MHz and 25.175MHz. Something else in your design is causing the problem when the frequency is changed, but without further information about the design and e.g. simulation results, there is no way of answering the question. \$\endgroup\$ Aug 24 at 20:16
  • \$\begingroup\$ How "deep" is your FIFO? That is, how many values can it store before it begins to lose data? \$\endgroup\$ Aug 25 at 6:16
  • \$\begingroup\$ Thanks for your input, I added some more context! \$\endgroup\$
    – TimSch
    Aug 25 at 16:32
  • \$\begingroup\$ Wait, you using a different clock for signal tap and the FIFO output? This will cause all sorts of weird behaviour. You ideally need the same clock for signal tap and the FIFO. You can have multiple signaltap instances - one for the write side and one for the read side. \$\endgroup\$ Aug 25 at 23:36


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