I'm confused whether the overdrive voltage for an NMOS/PMOS transistor is supposed to be $$V_{ov} = V_{gs}-V_t,$$ $$V_{ov} = V_{sg} - V_t,$$ or $$V_{ov} = V_{gs}-|V_t|$$

and whether it matters whether we're talking about an NMOS or a PMOS.

My professor's slides give the first equation in the context of NMOS's (as does the Wikipedia page on overdrive voltage generally), and I asked one of my TA's if the order of subtraction was just swapped for a PMOS, but he was really unclear and said something about taking the absolute value of \$V_t\$ if we're using \$V_{sg}\$ instead of \$V_{gs}\$.

For context, I was asking him whether I should be using \$0.4\$ or \$-0.4\$ in the following problem:

A PMOS has its source grounded and a threshold voltage of \$-0.5V\$. What should be the gate voltage in order for the device to operate with an overdrive voltage of \$|V_{ov}|=0.4V\$?

The absolute value part threw me off because it seems like there should be two solutions, but the TA said no, there's only one solution and that's because I should just take the absolute value \$V_t\$ and add it to \$|V_{ov}|\$, but was unclear about why or how I was supposed to know that.

What's the correct equation to use here so that I just get one solution for \$V_{gs}\$ instead of two? And what's the general sign convention for overdrive voltage in regards to NMOS vs PMOS devices that would determine that equation?


3 Answers 3


Here are an N-channel MOSFET, and a P-channel one in a simple setup to demonstrate the conditions required to switch their channels "on" and "off":


simulate this circuit – Schematic created using CircuitLab

Let's look at what happens to drain current \$I_D\$ for the N-channel device (left), as I sweep the source \$V_1\$ from 0V to 8V:

enter image description here

As would be expected, there's no drain current when the gate is at the same potential as the source, or in other words \$V_{GS} = V_G - V_S = 0V\$.

As \$V_1\$ rises, the gate becomes more and more positive with respect to the source (which is fixed at 0V), and at some point the channel begins to conduct. The left green marker shows where that occurs, the onset of channel conduction where \$I_D\$ begins to rise. We call this point the "threshold voltage" \$V_T\$, or more commonly \$V_{TH}\$ or \$V_{GS(TH)}\$.

The right green marker is some arbitrary voltage I've chosen to apply to the gate in order to saturate the transistor, to obtain close to the maximum possible \$I_D\$, and it's significantly higher than \$V_T\$. This additional voltage, over and above the threshold is "overdrive" \$V_{OV}\$.

At all times, the difference between gate potential \$V_G\$ and source potential \$V_S\$ is called \$V_{GS}\$, and from that graph you can see it is:

$$ V_{GS} = V_T + V_{OV} $$

Rearranging that to find \$V_{OV}\$ we get:

$$ V_{OV} = V_{GS} - V_T $$

This is pretty obvious for an N-channel MOSFET, but it doesn't prepare you for the sign confusion that comes free in every packet of P-channel MOSFETs.

Focussing on the right hand circuit containing the P-channel device, I will perform the same sweep on \$V_2\$ (from 0V to 8V):

enter image description here

I've tied the source to ground, \$V_S=0V\$, and the lower supply is now negative. This means that current still flows downwards (from higher potential to lower), but you'll notice that the arrow for \$I_D\$ points upwards. This is because "drain current" is defined to be current flowing into the drain. This is why current \$I_D\$ is negative in that graph, corresponding to a positive current downwards. I'll say more about this later.

Note: I'm forced to demonstrate this way by the simulator, because it doesn't permit me to sweep the gate from 0V to -2V

Pay close attention to what happens to gate potential \$V_G\$ as \$V_2\$ increases. \$V_G\$ actually falls in potential, becoming negative, since it's tied to the negative side of \$V_2\$, while \$V_2\$ positive is held at 0V. I ask you to imagine that the horizontal axis of that last graph corresponds to:

$$ V_{GS} = V_G - V_S = -V_2 - 0V = -V_2 $$

so that \$V_{GS}\$ starts at 0V at the left, and becomes increasingly more negative, all the way to \$V_{GS}=-8V\$ on the right. That is, replace all positive numbers with negative, and treat the horizontal axis as representing \$V_{GS}\$.

Now, from that graph, the left hand marker shows \$V_T = -2.0V\$ the value of \$V_{GS}\$ necessary for the channel to just begin to conduct. The right hand marker shows the value \$V_{GS} = -3.5V\$, which I am currently applying to saturate the transistor. The difference between those two values is the "overdrive" \$V_{OV}\$:

$$ \begin{aligned} V_{OV} &= V_{GS} - V_T \\ \\ &= (-3.5V) - (-2.0V) \\ \\ &= -1.5V \end{aligned} $$

As you can see, the same formula \$V_{OV} = V_{GS} - V_T\$ is still valid, but only if you are careful to keep all the signs correct.

For P-channel devices, gate potential \$V_G\$ must be more negative than source \$V_S\$ to switch the transistor on, and in keeping with the convention that \$V_{GS} = V_G - V_S\$, that means (strictly speaking) that \$V_{GS}\$ is negative. This is why (for P-channel) \$V_T\$ (\$V_{GS(TH)}\$) is usually quoted in the datasheets as a negative quantity, and your value for \$V_{OV}\$ should also be negative. As long as \$V_{GS}\$, \$V_T\$ and \$V_{OV}\$ all have the same sign, the formula you referred to still works.

Perhaps, then, it would be easier for you to follow these ideas:

  1. Consider \$V_T\$ as the value of \$V_{GS}\$ necessary to begin switching on.
    • For N-channel MOSFETS, \$V_T\$ is positive.
    • For P-channel MOSFETS, \$V_T\$ is negative.
  2. Consider \$V_{OV}\$ to be the "extra" potential beyond \$V_T\$ needed at the gate to take it from "barely conducting" to "fully conducting".
    • For N-channel MOSFETS, \$V_{OV}\$ is positive, and when added to \$V_T\$, it pushes \$V_{GS}\$ even more positive
    • For P-channel MOSFETS, \$V_{OV}\$ is negative, and when added to \$V_T\$, it makes \$V_{GS}\$ even more negative

I am personally guilty of lazily quoting P-channel \$V_{GS}\$ as positive, completely contrary to the conventions that I just described, but when I do so, I'm also careful to quote a positive \$V_{GS(TH)}\$ and positive \$V_{OV}\$. I have to trust that the reader understands that, actually, the numbers should be negative, and I'm just being lazy.

In P-channel MOSFET datasheets, you see quoted vales for \$I_D\$, \$V_{GS}\$ \$V_{DS}\$ etc as negative. Here's a graph of \$I_D\$ versus \$V_{GS}\$ from the datasheet of the IRF9530, a P-channel device, and an excerpt from its table of electrical specifications:

enter image description here enter image description here

Notice the negatives (in the red boxes) on the graph axes, and how all the values are negative in the table. Since I know that this is a P-channel device, I tend to ignore those negative signs, and work with positive values in my head, because I find that easier to do, but I'm always aware that for this device to be switched on, in reality the gate will have to be more negative than the source, and negative \$I_D\$ corresponds to positive current flowing from source to drain, emerging out of the drain.

Datasheets strive to conform strictly to convention. Those conventions include:

  • \$V_{XY}\$ always means \$V_X - V_Y\$, and not the other way around. Therefore if \$V_{XY}\$ is positive, then \$V_X > V_Y\$ and vice versa.

  • \$I_X\$ always refers to current flowing into node X. If \$I_X\$ is negative, this is the same as \$|I_X|\$ in the opposite direction.


Usually, for NMOS you'll see \$V_t\$ given as a positive value and for a PMOS \$V_t\$ will be given as a negative number, used to remind you that it's a PMOS.

Your second equation is wrong for PMOS, because you will have a negative \$V_{gs}\$ when on, and then subtract a positive \$V_t\$, resulting in a much higher overdrive than expected.

The equation that I was taught for PMOS was

$$V_{ov} = V_{sg} - |V_t|$$

This maintains that the transistor is on when \$V_{ov}\$ is greater than zero, and lets you use similar equations for PMOS as for NMOS as long as you swap the position of the (gate and source) and the (gate and source) to keep your voltages positive. Technically, yes, this will give two answers for \$V_t\$ if you need to solve for it, but remember it assumes a negative \$V_t\$ because it's PMOS.

You could instead use \$V_{gs}\$ and negative \$V_t\$, but that'd mean you'd need to have different rules for when a transistor is in the different regions since everything is negative now. So long as you remain consistent, you should be fine.

  • \$\begingroup\$ Hmmm. So basically, we only have the absolute value around \$V_t\$ for the PMOS equation because we artificially impose a negative sign on \$V_t\$ for PMOS? \$\endgroup\$ Aug 25, 2023 at 2:04
  • 1
    \$\begingroup\$ Yep. It's artificially imposed so that the math works out if you use \$V_{gs}\$ for everything, but to avoid negative numbers (and make it analogous to PMOS) you can instead use \$|V_t|\$ and \$V_{sg}\$. Sedra/Smith uses the \$|V_t|\$ way, I don't know about other textbooks. \$\endgroup\$
    – Reid
    Aug 25, 2023 at 2:22

I'd actually argue that the problem is ill-posed if the professor is looking for an answer that is a single value for \$V_{gs}\$.

I believe he's using the absolute value to account for:

  • when a student uses either formula where \$V_{gs}\$ will be negative for a PMOS
  • or, for the formula where \$V_{sg}\$ is used, where this value will be positive.

In doing so, if you apply the absolute value rigorously to the formulas above, you'll end up with 2 different solutions for the gate voltage.

You'll be in for a shock if you knew that \$V_{ov}\$ can be negative in a real design environment, and it doesn't necessarily mean the transistor is in the linear region or cut-off. Before a transistor goes to those regions from being in saturation, there is the weak-inversion region, which is how most CMOS integrated circuits are designed nowadays.

In other words, for a given transistor, if \$V_{gs}\$ is higher or lower than \$|V_t|\$ by 0.02V, for example, it can be in the weak-inversion region and work pretty well as a linear amplifier (assuming there's proper biasing and negative-feedback around, of course).

That is the rigorous view of the situation.

However, if you're not yet up to that level in your university, your professor is, most likely, looking for a \$V_{ov}\$ that implies, always, that \$|V_{gs}|\$ is required to be bigger than \$|V_t|\$. Perhaps he used the absolute value notation to account for the different formulas given.

If so, then, use:

$$ V_{ov}=0.4=V_{sg}-|V_t| $$ or $$ V_{ov}=-0.4=V_{gs}-V_t $$

In this last one, \$V_{gs}\$ is negative, because \$V_{gs} = V_g - V_s\$ (duh!). In both formulas, \$V_t=-0.4V\$ will lead to the correct result for the PMOS.


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