Strange plot of voltage source in CMOS inverter circuit simulation

Question

I made a simple simulation of a CMOS inverter in everycircuit and the results look reasonable enough when I just plot the voltages on the input and output nodes. But, for some reason, the voltage plot of the actual input source looks completely different than the plot for the input node:

In case it's not clear from the image: the purple plot is for the input node, the green the output node, and the red the input voltage source.

It seems incredibly weird that the voltage plot for the source itself wouldn't match that of the node it's connected to. Is this just a bug in the simulator and I should disregard that plot, or is there some reason the red plot really should look like that?

Answer 1

You're looking at the source current (check the units on the right y-axis).

The CMOS gate has high impedance, so you see a rather small current flowing out of your voltage source into the CMOS inverter gate.

CMOS inverters have a parasitic gate-to-drain capacitance, \$C_{gd}\$. You can imagine that if this inverter were a linear amplifier, this \$C_{gd}\$ would actually short the voltage transfer at high frequencies, thus reducing the gain of the amplifier.

The \$\frac{dV}{dT}\$ of the device is rather large when the voltage transition happens (when switching the output from 0V to 1V or vice versa). We know that \$I_{C}=C\frac{dV}{dT}\$, so there will be a larger current in that region of the output voltage curve.