I'm trying to understand the SMPS operation. enter image description here

  1. The goal is to select inductor (L1) & capacitor (C1) values that satisfy the working condition below.
  • V1: 22-26 V range.
  • Power supply required: 1 A.
  • Ripple voltage less than 100 mV.
  • Frequency of oscillator 100 kHz.
  • VI(limit) is set such that MOSFET is turned off when the current exceeds 2.5 A.

I'm using the method below

Vin=24V, Vout=12V Vout-ripple=100mV

Peak to peak inductor ripple current (ΔIL): Vout ripple/Vout=0.0083

Duty Cycle: Vout/Vin=0.5

Inductor (L)=(1-D)*Vin/(f.ΔIL) =(.5)(24)/(100kHz)(0.0083)=0.0144

The inductor value is not correct. I believe my mistake is on the switching frequency. kindly let me know how to calculate the switching frequency.

thank you

  • 3
    \$\begingroup\$ Is this an academic assignment? \$\endgroup\$ Aug 27, 2023 at 4:52
  • \$\begingroup\$ Is there supposed to be a resistor that V_I(LIMIT) is compared to? Or a driver between the flip-flop and NMOS? Or a ground-referenced feedback node? (Hm maybe not, that should still regulate; albeit poorly.) \$\endgroup\$ Aug 27, 2023 at 5:49
  • \$\begingroup\$ Welcome! For homework questions, you are required to show your own effort at solving it. We can help if you are stuck. “Plz solve it for me e-Z quick man” type of questions are closed. \$\endgroup\$
    – winny
    Aug 27, 2023 at 7:47
  • \$\begingroup\$ Thanks for the edits! "Peak to peak inductor ripple current (ΔIL):" -- missing value? So, what's wrong with the inductor value? Also, what units is that in? \$\endgroup\$ Sep 2, 2023 at 6:28
  • 1
    \$\begingroup\$ I am repeating Tim Williams question about the apparent absence of a current sense resistor. How is current to be limited if it is not sensed? \$\endgroup\$ Sep 2, 2023 at 22:01

2 Answers 2


Type of SMPS: buck converter. Why? Because Vout can only get as high as V1 at most, not higher (hence it "bucks" or "reduces" the input voltage).

As for the rest of your questions: happy to help, but am reluctant to do so if you cannot demonstrate that this is not an academic assignment part of your education.

PS: The method of measuring the current seems dubious.

UPDATE 2023-09-02
I have made this update to my answer to express some concerns I have with this circuit, and hopefully to help you understand the behaviour of this circuit. Please refer to the schematic below, which is the schematic you submitted in the OP to which I have added mark-ups (in blue) as follows:
a) identifiers for all components.
b) identifiers for important nodes.
c) added load resistor, R3.

Schematic of OP, with my mark-ups

My question to the OP is: Do you understand how this circuit works? Allow to me provide some assistance here, and also to try to explain why I have concerns. Let's assume this is a switch-mode power supply (SMPS) as per the heading of your post. This means the main switching device, Q1 (shown as a MOSFET on your schematic) can only be in one of two possible states: ON, or OFF. So it is very important to understand what causes Q1 to change from (a) OFF to ON, and (b) from ON to OFF.

Q1 changes from OFF to ON
Let's consider how this circuit will behave when Q1 is OFF, the inductor current is zero, and the output voltage is close to the target value of 12V.

N5 is responsible for turning Q1 ON and OFF. What causes N5 to turn on Q1? Well, it would be the signal at the input to N5 labelled S, which we shall assume is asserted when input S is driven HI. N5 is a Set/Reset flip-flop, its output Q will go high and stay high when S is driven high, and its output Q will go low and stay low when R is driven high.

N5 input S is driven by logic gate N4 - unfortunately, I cannot tell if N4 is an AND gate, or an OR gate because the way it is drawn is confusing; assuming it is intended to be one of these (perhaps you intended it to be something else?), then here are the standard symbols for AND and OR logic gates:

Logic gates, AND, OR, from Wikipedia

N4 Case #1:
In the case where N4 is an AND gate: to turn Q1 ON, N3 output must be HI, and N2 output must be LOW at the same time. N2 output is LO only when voltage at X3 is lower than the voltage at X5. Let's assume X5 is a constant voltage wrt X1. So that means N2 monitors the output voltage via D2, C2, R1 & R2, and N2 output goes LO when [Vout] falls below a certain threshold value. After N2 output goes LO, Q1 turn-on then occurs at the next clock edge (a low-to-high transition at N3 output).

N4 Case #2:
In the case where N4 is an OR gate: to turn Q1 ON, N3 output must be HI, or N2 output must be LOW. So Q1 turn-on occurs either at a clock edge from N3, or when N2 output goes LO, which ever occurs first.

I hope you can see that the behaviour of the circuit will be very different for Case 1 and Case 2.

Q1 changes from ON to OFF
OK, now lets assume that Q1 has been turned on, and which causes node X1 to now be connected to node marked [Vdd=24V]. Since [Vout]=12V, the voltage across L1 is now positive, and current will start to flow from V1 to C1 via Q1 and L1. L1 current will ramp up at a fixed slope set by: di/dt = (V1 - Vout) / L1.

N5 has been latched to the SET state, and will stay that way until a HI occurs at its input marked "R", which is the output of N1.

So we must ask the next obvious question: what causes N1 output to go HI?

Well, for N1 output to go HI, the voltage at X4 must be higher than the voltage at X6. Hmmm... can you see the problem here? What is the voltage at X4? Does it contain any information regarding the current through Q1? And what is the votlage at X6? Is it like the X5, a constant voltage wrt X1?

Well, perhaps we can take a clue from this part of your post:

VI(limit) is set such that MOSFET is turned off when the current exceeds 2.5 A.

So let's interpret this to mean that when Q1 is turned on, it then remains on until its current reaches 2.5A, at which point it is then turned off.

So here is a question for you to consider - what impact does [Vout] have on when Q1 is turned off? The answer seems to be: it has no impact at all. Only the current in Q1 (which is the same as the current in L1) affects the turn-off.

So at the moment of Q1 turn-off, what is the state of the circuit? Well, we know that L1 is carrying 2.5A, and Vout is some value probably higher than target of 12V (but we don't know this for sure). The voltage across the iductote has now reversed polarity (X1 voltage is close to 0V, while voltage across C1 has not changed dramatically - it is still about 12V, perhaps a little higher, say 12.05V. This causes the inductor current to start to ramp down, again with almost constant rate of change.

The circuit will now stay in this state until something causes N5 to change state which then turns on Q1 - please refer back to section headed "Q1 changes from OFF to ON", except now the inductor is not zero.

Can you clarify how the circuit behaves, in particular:

  1. What causes Q1 to turn off, ie: what causes output of N1 to go hi.
  2. What type of gate is N4.
  3. What causes output of N2 to go low.
  4. What is the waveform at N3 output, eg: is it a PWM with a low duty cycle (a short hi pulse with a long lo) or something else.

You're assuming wrong things about what this question is meant to test. The circuit won't work properly as shown. You have to fix it up first so that it'll work. Only then you can calculate stuff.

The steps for you to take are:

  1. Figure out how this topology of a SMPS controller should look like.

  2. Fix the schematic up so that it works.

  3. Derive or look up the design equations.

  4. Calculate the necessary component values.

Any of the variety of well-written application notes from companies that make power converter chips should cover this topology and the controller type well. Look for app notes from companies with good history of technical publishing - TI, Analog, Maxim, ONsemi, Toshiba, to make it easier for you. Do not look up random stuff on internet about power converter design, because half of it is either outright wrong or subtly misleading or just a paraphrase from a better source, but without attribution and without understanding. Caveat emptor - start with known good sources.

What type of SMPS is this?

There are two "types" or topologies here - both are important:

  • the converter topology - the arrangement of the components in the power path,
  • the controller architecture - the arrangement of the components that control the power path's switching.

You'll need answers for both of those.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.