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I know that a Schmitt-trigger makes rising edge of an input pulse sharper.

But is the rise time of the output pulse affected by the input’s rise time? How can this be shown by simulation or shown mathematically with an example?

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  • \$\begingroup\$ I take it you're not asking about the ideal component. In that case specifying at least the logic family would narrow the answers to something specific. \$\endgroup\$ Sep 1, 2023 at 10:59

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Yes, it will likely be affected somewhat. Intuitively you would expect that because at slow input change rate you are depending on the positive feedback to drive the output slew rate. For a fast input transition that may be bypassed.

As an example, we can simulate a common CMOS ST circuit in LTspice using the default NMOS/PMOS elements:

enter image description here

I've added two parasitic elements - C1, a 1pF load capacitance and R1 a 10Ω input resistance.

Simulated 1usec rise time at the input leads to 131ns fall time at the output (90% to 10%)

Simulated 10usec rise time at the input leads to 344ns fall time at the output (90% to 10%)

enter image description here

If there was an inverter or two at the output the difference might not be so easy to see due to the increased gain.

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I know that a Schmitt-trigger makes rising edge of an input pulse sharper.

A schmitt-trigger makes a transition that is not related to the rise time of an input transition, it is strictly related to the voltage level of the transition. However there is also hysteresis, so you don't get a lot of unwanted transitions with noisy signals.

The output rise time of a schmitt trigger is based off of the part and the internal construction of the output transistor stage, so if you are designing with a schmitt trigger look at the hysteresis levels to see where it will transition on the input voltages. Look at the rise times in the datasheet for the output transition times (will also somewhat depend on the load). Usually the datasheet will have test case circuits that you could use to calculate or simulate with. Another thing is looking to see if the manufacturer has a spice file to simulate with.

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  • \$\begingroup\$ Load capacitanve also affects output rise and fall times. \$\endgroup\$
    – RussellH
    Aug 31, 2023 at 0:21
  • \$\begingroup\$ So do you mean output risetime is independent from input risetime? \$\endgroup\$
    – GNZ
    Aug 31, 2023 at 1:44
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In a well-made one, no.

Note that, for a transfer function with a hysteresis loop, ideally it's very square, i.e. the output stays valid-low for any input below the switching threshold, and valid-high for any input above.

For a simple schmitt trigger like the two-transistor circuit,

BJT schmitt trigger

From: BJT schmitt trigger threshold voltage calculation

this may not be the case. Suppose the input and output are low; raise the input slowly. As it goes up, Q1 begins to turn on, V(RE) rises, and Q1 collector voltage falls. Vo saturates to V(RE) at the lowest, so, it starts to rise as well. Eventually, insufficient base bias (from Q1-C through RB2) causes Q2 to turn off; Vo jumps up and V(RE) falls a bit (now being supplied only through Q1). V(RE) falling, of course, reinforces Q1's on-ness, hence the hysteresis loop. A similar set of conditions applies for the high-to-low transition.

That is, the transfer function generally looks something like this:

Hysteresis loop

The region where Vo is varying with Vin could be called a "softness" of the curve.

If such a circuit is followed by sufficient gain, so that the sudden switching across the hysteresis loop is amplified into a flat square wave, you have a nice reliable schmitt trigger. Logic chips do this, also to improve output drive strength, and to make the internal state independent of output loading.

As it happens, this circuit does rather well, with the "soft" regions being typically like 5% of the total output swing. Devices with lower gain, like MOSFETs, or the vacuum tubes its inventor Schmitt worked with, will show more "softness".

If you have a trigger circuit so "soft" that the rise/fall time is affected (i.e., encroaching on the 10-90% or 20-80% range that's being used to measure edge time), then input transition rate will affect output edge rate some. The correspondence will be less than proportional, because the hysteresis loop hard subtracts a chunk of the input ramp.

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  • \$\begingroup\$ What dou you mean by soft region? \$\endgroup\$
    – GNZ
    Aug 31, 2023 at 7:42
  • \$\begingroup\$ Figured I wasn't going to get away with a verbal description... See edit @GNZ \$\endgroup\$ Aug 31, 2023 at 8:02
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is the rise time of the output pulse affected by the input’s rise time?

Shorter answer: No.

Not if it's done right. The output edge rate is determined by the characteristics of the transistors used in the circuit. Some parts have larger or smaller values of the internal capacitances. The smaller the capacitors, the "faster" the transistors.

Transistors for RF and other high-frequency applications have smaller internal capacitances, and their values often are on the datasheets. For jellybean parts, not so much, which makes accurate simulation very difficult.

Other circuit factors, such as stray capacitances and whether or not the resistors have a "non-inductive" construction, also affect the output edge rate, but usually it is the transistor characteristics that are the major determining factor.

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If the input to a well-designed Schmitt trigger increases or decreases monotonically through the hysteresis region, the output will snap cleanly. If there is noise on the input, however, which causes it to reach the switching threshold but not stay above it long enough to switch fully, the trigger may enter what's called a metastable state.

If at some point after entering a metastable state, the input rises above the upper switching threshold and stays there long enough to switch, the device will register the input as high. If it falls below the lower threshold and stays there long enough, the device will register the input as a low. Until one of those things happens, however, the device may sit in a perfectly balanced state which might settle to either a clean high or a clean low after an arbitrarily long time.

It's possible to bias a device so that any balanced or metastable state will always output low, or so that any such state will always output high, or to have a pair of outputs representing "definitely high" or "definitely low". Even the latter course of action won't completely solve metastability, however, since it would be possible for a "definitely high" output to become active just as the device's input is about to switch become definitely low, resulting in a "runt pulse" on the "definitely high" output. The best one can do is design a circuit so that an arbitrary number of runt pulses on the "definitely low" or "definitely high" output won't affect things if every pair of consecutive pulses on one of the outputs either has no pulses on the other output, or at least one valid pulse on the other output. If one does that, the Schmitt trigger can be replaced with simple threshold detectors.

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  • \$\begingroup\$ (...which causes it...Do you intend line breaks where there are double blanks before Ifs? add a newline.) \$\endgroup\$
    – greybeard
    Aug 31, 2023 at 17:00
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Short answer

Normally the input rise time is much longer than the output rise time (a Schmitt trigger is designed to work with slowly changing input signals) so at the time of switching it is assumed that the input voltage does not change. A very good mechanical analogy is the trigger of a gun - we pull it slowly until it fires; then we lose control of it.

However, if the input signal starts to change rapidly (commensurate with the speed of the output signal), this only improves the switching speed. How can this be explained?

Explanation

What "hysteresis" is

To understand this phenomenon, we need to have a good intuitive understanding of the so-called "hysteresis". This is when a switching element changes its threshold at the time of switching to help the input signal.

How to implement hysteresis

In the classic transistor Schmitt trigger, this is implemented by the differential input (base-emitter junction) of the input transistor. In fact, there are two single-ended inputs - the first of them (base) is controlled by the input voltage source, and the second (emitter) by the trigger output.

Operation

Vb increases, Ve constant: Let's assume that the input (base) voltage Vb slowly increases, trying to reach the threshold (emitter) voltage Ve which stays constant. The trigger behaves as a device with a single-ended inverting input.

Vb constant, Ve decreases: When this happens, Ve begins to decrease sharply and Vb remains practically constant for the transition duration. The trigger behaves as a device with a single-ended non-inverting input.

Vb increases, Ve decreases: But if Vb sharply increases while Ve sharply decreases, the trigger behaves as a device with a differential input. As a result, the switching speed should be even faster. In the mechanical "gun trigger" analogy this means to pull the trigger at a speed close to that of the mechanism :-)

Conclusion

The rise time of the Schmitt trigger input signal would have some (increasing) effect on the switching speed if it were commensurate with the rise time of the output signal. However, this has no practical value.

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