Currently I am working on PCB layout of previous question asked on this site.

This board has only 2 layers and will be produced as an home-made prototype.

Voltage: 12V
Current: 1A

This is the electric lock matrix traces in design. As you can see on picture there are several NMOS which control current flow of the columns to GND (blue traces; bottom layer).

Later I am going to add so called bootstrap PMOS (if I am not mistaken) control over the rows flow of 12V power to electric lock (red traces; top layer).

Routing nmos control


  • Those traces are crossing each other perpendicularly. Is this generating EMI issues?

  • Is it better to use power planes such this on the picture or try to use normal traces 1.0mm?

  • If this design is completely wrong - what and how should I change?


Based on the answer adjustments have been made in the design. Redesign

Tried to keep spacing between the traces.


Would you like to point out the mistake which could have been made in this redesigned version?


  • Since those (blue) connections are on bottom layer, I would appireciate help in guidline for GND plane creation.

  • How should i concider switching speed for EMI design? This matrix controll only electric locks, which need about 1s to archieve 900mA which is going to be sustained for about 5s. Only one lock at time.

  • Return path is to GND I assume

  • \$\begingroup\$ On your second layout, I would route the short 45 degree blue tracks hoprizontally rather than at 45 degrees (maybe except the bottom segments). I have seen claims that acute angles between tracks can cause etching problems. \$\endgroup\$ Commented Sep 1, 2023 at 0:34
  • \$\begingroup\$ Hello Peter, thanks for reply. Indeed, I had also heard about that. For sure i need to change this COM0A, and make some proper adjustments \$\endgroup\$
    – Alioth
    Commented Sep 1, 2023 at 7:16
  • \$\begingroup\$ @PeterBennett at these sizes, in modern processes, I'd yet to see a problem with that. It's not like someone would cut this out with a craft knife out of vinyl foil or something :) yes, an etching process can't make arbitrarily acute angles, but so what, there'd by a couple µm of unintended rounding here, which isn't a bad thing here. \$\endgroup\$ Commented Sep 3, 2023 at 16:48

1 Answer 1


Is it better to use power planes such this on the picture or try to use normal traces 1.0mm?

This calls for traces that are wide enough for the job. You can certainly manually draw planes as if you're designing circuit boards in the 1950s; but since you're not: 1.0mm sounds wide enough for 1A, more doesn't hurt, you have the space. Using traces would also make this prettier (by not having nearly square planes), and most importantly, are easier to do, and allow your layout program to check whether you've done things correctly.

So, yeah, remove these planes, simply add a trace class of the desired width, assign the relevant nets to that trace class, and connect the components.

Those traces are crossing each other perpendicularly. Is this generating EMI issues?

How should we know without knowing how rapidly you switch whether something causes EMI?

No, perpendicularity in it self doesn't hurt. You need to ensure a good current return path, that's the critical thing. We can't read from this slightly confusing excerpt of your layout where your current flows in total, so we can't really advice on that, other than the general: your current return path should be good.

  • \$\begingroup\$ Thank you for your answer @Marcus Müller. Made some adjustments based on your guidlines. I would be delighted if you could help me to understand how to achieve proper return path and if I am not mistaken proper GND plane. \$\endgroup\$
    – Alioth
    Commented Aug 31, 2023 at 20:55
  • \$\begingroup\$ I was recently directed to this Rick Hartley video, which is a real eye-opener about how the current moves across a board. Thanks @RussellH! \$\endgroup\$
    – jonathanjo
    Commented Sep 1, 2023 at 13:58
  • \$\begingroup\$ @jonathanjo yeah need to watch this. Also recommended in phil's lab channel to watch this assume i have to. \$\endgroup\$
    – Alioth
    Commented Sep 3, 2023 at 15:59

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