Currently I am working on PCB layout of previous question asked on this site.
This board has only 2 layers and will be produced as an home-made prototype.
This is the electric lock matrix traces in design. As you can see on picture there are several NMOS which control current flow of the columns to GND (blue traces; bottom layer).
Later I am going to add so called bootstrap PMOS (if I am not mistaken) control over the rows flow of 12V power to electric lock (red traces; top layer).
Those traces are crossing each other perpendicularly. Is this generating EMI issues?
Is it better to use power planes such this on the picture or try to use normal traces 1.0mm?
If this design is completely wrong - what and how should I change?
Tried to keep spacing between the traces.
Would you like to point out the mistake which could have been made in this redesigned version?
Since those (blue) connections are on bottom layer, I would appireciate help in guidline for GND plane creation.
How should i concider switching speed for EMI design? This matrix controll only electric locks, which need about 1s to archieve 900mA which is going to be sustained for about 5s. Only one lock at time.
Return path is to GND I assume