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I have a module I'm writing in Verilog that effectively contains a 16 by 10 2D array. At a given point and "row", what I want is to have that data pushed to a net that can be read outside of the module, however, when I attempt to use a variable input to determine which row I want my synthesizer returns these errors:

Error (10734): Verilog HDL error at FontRom.v(12): ROW_NUM is not a constant

The error is pretty clear, but now I'm not sure how I can access different parts of the array if I'm not allowed to use a variable. Also, typically when I need to preload a reg with data I have a reset condition that does it, do I have to do the same thing in this case also? Below is my code. Thank you.

module FontRom(CLK, CHAR_IN, ROW_NUM, DATA_OUT);
   input    wire  [7:0]  CHAR_IN;
   input    wire  [3:0]  ROW_NUM;
   input    wire         CLK;
   output   reg   [0:9]  DATA_OUT;

   parameter   char       = 2'h48;
   parameter   font_value = 40'h000008120481204813FC81204812048120400000;

   reg [0:159] char_font  = font_value;

   always @(negedge CLK)
      if (CHAR_IN == char) begin
         DATA_OUT = char_font[2*ROW_NUM:2*ROW_NUM+10]; // +10 due to Big Endian
      end
      else begin
         DATA_OUT = 8'bZZ;
      end
endmodule
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  • \$\begingroup\$ You don't need char_font at all, I think: you can just select a value from font_value directly. dwikle has a very good answer on how to do the array select. \$\endgroup\$ – pjc50 May 2 '13 at 22:14
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Part selects in Verilog can use variables, as long as the width of the select is a constant. The solution here is to user a lesser-known part select syntax, where you specify the offset and the size.

DATA_OUT = char_font[2*ROW_NUM+:10]; // +10 due to Big Endian

The above selects 10 bits starting at bit 2*ROW_NUM


Excerpt from the SystemVerilog LRM, IEEE 1800-2012

An indexed part-select is given with the following syntax:

logic [15:0] down_vect;
logic [0:15] up_vect;

down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]

down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]

The msb_base_expr and lsb_base_expr shall be integer expressions, and the width_expr shall be a positive constant integer expression. Each of these expressions shall be evaluated in a self-determined context. The lsb_base_expr and msb_base_expr can vary at run time. The first two examples select bits starting at the base and ascending the bit range. The number of bits selected is equal to the width expression. The second two examples select bits starting at the base and descending the bit range.

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  • \$\begingroup\$ Brilliant, that worked! That is some different looking syntax, I thought you had a typo in there at first with respect to where that + is. The excerpt is pretty clear then that a constant width must always be specified, but in the future, in case I need to, does this mean that one cannot use two variables in order to dynamically access a single point in a 2D array at all? Or is there a different expression for that? \$\endgroup\$ – Jon.H May 4 '13 at 4:31
  • \$\begingroup\$ You can use two variables to access a single value from a 2D array, as long as the bit width of the value selected is a constant. E.g. to select a single bit from a word within an array of 8-bit words, you can do x = mem[word][bit] \$\endgroup\$ – dwikle May 6 '13 at 14:22
  • \$\begingroup\$ Vector selects [offset +: wdith] is also valid Verilog 2001 syntax \$\endgroup\$ – shuckc May 17 '13 at 14:31

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