I have a module I'm writing in Verilog that effectively contains a 16 by 10 2D array. At a given point and "row", what I want is to have that data pushed to a net that can be read outside of the module, however, when I attempt to use a variable input to determine which row I want my synthesizer returns these errors:
Error (10734): Verilog HDL error at FontRom.v(12): ROW_NUM is not a constant
The error is pretty clear, but now I'm not sure how I can access different parts of the array if I'm not allowed to use a variable. Also, typically when I need to preload a reg with data I have a reset condition that does it, do I have to do the same thing in this case also? Below is my code. Thank you.
module FontRom(CLK, CHAR_IN, ROW_NUM, DATA_OUT); input wire [7:0] CHAR_IN; input wire [3:0] ROW_NUM; input wire CLK; output reg [0:9] DATA_OUT; parameter char = 2'h48; parameter font_value = 40'h000008120481204813FC81204812048120400000; reg [0:159] char_font = font_value; always @(negedge CLK) if (CHAR_IN == char) begin DATA_OUT = char_font[2*ROW_NUM:2*ROW_NUM+10]; // +10 due to Big Endian end else begin DATA_OUT = 8'bZZ; end endmodule