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This exercise from Introduction to Computing Systems from Bits and Gates to C/C++ & Beyond by Yale N. Patt and Sanjay J. Pattel asks what the value of OUT signifies in this circuit. If it's 0, then there are many cases that give 0, same for 1. So, am I supposed to study all these cases (which is a LOT of work that I don't think is the goal of the exercise)? And if I did so and found out what combinations give 0 and those that give 1, how will this help me find the significance of OUT. Moreover, they didn't even tell what the circuit does, nor what IR, P, Z and N on the top of the circuit are, probably registers but they also didn't tell what they are meant for, so how am I supposed to know the significance of OUT without knowing all of what I mentioned?

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    \$\begingroup\$ P, Z, and N are likely ALU status: parity, zero, and negative. The IR is likely an instruction register, by the looks of which is longer than 8 bits and perhaps 16 bits or longer. Don't have and never read that book/exercise. So I can only give a wild guess. If I had to guess about the meaning of that, I'd say that there is an instruction type that needs to output a control bit (out) that controls something in the execution phase that we don't know about but where controlling it relies upon some fields in the instruction as well as sampling those three status bits. Maybe a conditional JMP? \$\endgroup\$
    – periblepsis
    Sep 2 at 23:37
  • \$\begingroup\$ @periblepsis maybe but the book didn't talk about such things before at all so this shouldn't be an exercise at this point of the book \$\endgroup\$
    – oabdullae
    Sep 3 at 0:40
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    \$\begingroup\$ I wouldn't know, of course. Anyway, ignorant as I truly am about the circumstances, what I wrote is what I'd guess. Luckily, you have the materials. So you are in the better position to figure it out. \$\endgroup\$
    – periblepsis
    Sep 3 at 1:12
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    \$\begingroup\$ @oabdullae I looked at that book. It's very, very poorly written, and leaves out a lot of explanation and description that it'd need to make sense to a non-expert. I'd say that book is a waste of paper it's printed on. If you don't have to use that book, throw it away and get something better. With a well-written book you wouldn't be asking questions here so often. \$\endgroup\$
    – Kuba hasn't forgotten Monica
    Sep 3 at 2:24
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    \$\begingroup\$ the book didn't talk about such things before at all so this shouldn't be an exercise at this point of the book You're assuming that the book was done by competent people. It wasn't. The answer to the question is rather simple to someone with knowledge in the field, but even then the question is somewhat pointless, since it's more of a "can you recognize this from what you've seen before". You'd be surprised at how much knowledge is needed to get this question answered. The book is not much help with it. \$\endgroup\$
    – Kuba hasn't forgotten Monica
    Sep 3 at 2:27

2 Answers 2

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With a background in many processors and their instruction sets, my conclusions are:

  • IR commonly means "instruction register".
  • P usually designates the parity flag in a processor's status set.
  • Z usually designates the zero flag in a processor's status set.
  • N usually designates the sign flag in a processor's status set (n for "negative").

The logic circuitry NORs the left 4 bits of the IR together, so that the output of the NOR is true only if all 4 bits are zero.

Each of the 3 next bits to the right is individually ANDed with one of the mentioned flags of the status set. Thus such a bit gates the flag. The outputs of the 3 ANDs are ORed together, which means that any of them can to be true to drive the last AND.

This last AND outputs true only, if the instruction in the IR has its 4 leftmost bits at zero and at least one of the next 3 bits is true and the respective flag is also true. Else the output is false.

One could now try to find some existing instruction set, but I don't see the necessity.

We can safely assume that this is the first part of the instruction decoder for condition jumps or branches or skips or a group of other conditional operations. For example:

binary opcode mnemonic meaning
0000 000 ... jn jump never (yes, there are such instructions sets!)
0000 100 ... jm jump on minus
0000 010 ... jz jump on zero
0000 110 ... jnp jump on not positive (negative or zero)
0000 001 ... jpe
(or jpo)		 jump on parity even
(could also be jump on parity odd, depending on the definition of P)

For simplicity they designed this simple mask scheme, which might allow only one of set mask bit. Combinations are possible, but some are ... hrm ... strange.

Final line: So OUT signifies the condition of a conditional command. It does not have to be an operation to change the flow of control, though!

Note: If the book really does not prepare you for this question (I didn't read it), you should consider to drop it and read another one.

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  • \$\begingroup\$ Thanks so much! Though I don't exactly know what condition jumps are (probably while loops in programming I guess) nor branches or skips. Anyways, what I understood is that this circuit does what a row in your table does. Am I right? Also what book can you recommend for me that treats the same topic as this. Thanks again :) \$\endgroup\$
    – oabdullae
    Sep 4 at 20:15
  • \$\begingroup\$ @oabdullae If you don't know what conditional jumps are, either you did not read the book or it is worse than assumed. -- You should do your own extensive web research. Recommendations are off-topic here. However, years ago I stumbled over "NAND2Tetris", it might be a start. \$\endgroup\$
    – the busybee
    Sep 5 at 5:43
  • \$\begingroup\$ I read the first 3 chapters of the book and still going on. ok I will look for this one, thanks \$\endgroup\$
    – oabdullae
    Sep 5 at 12:01
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Observations:

  1. IR is the instruction register.
  2. P, Z, N are bits in the status register.
  3. P, Z, N are each and-ed with a dedicated mask bit in the IR.
  4. The left 4 bits of the IR are AND-ed together.

The output is true when:

  • the left 4 bits of the IR are zero, since only then the 4-input NOR will output 1, and
  • any of the flags gated by the 3 right bits in the IR are set.

The output is false otherwise.

As for what does the output signify: nothing useful. The flag "masking" scheme as shown is useless. This is not, for example, how you'd decode a conditional jump, even though the authors probably had that intention.

The circuit's function can be exactly described, as above, but it is a useless circuit. Make your own conclusions from that.

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  • \$\begingroup\$ Your analysis on the book seems correct. However, since you used your apparent experience in machine code, you might want to go one more step. The output signifies the condition of a group of conditional jumps/branches/skips (execute if status bit X is set). These opcodes have the leftmost 4 bits at zero, and the next 3 bits define the status bit that needs to be set. For simplicity they design this simple mask scheme, which might allow only one of set mask bit. One could try to find some existing instruction set, but I don't see the necessity. \$\endgroup\$
    – the busybee
    Sep 3 at 8:54
  • \$\begingroup\$ I don't know if it's an error or a misunderstanding from me, but you said that "the left 4 bits of IR are ANDed together", which is not true because they are NORed. thanks for your answer though it was helpful :) \$\endgroup\$
    – oabdullae
    Sep 4 at 15:51
  • \$\begingroup\$ @thebusybee Can you please write a detailed answer explaining what you mentioned in your comment. Thanks! \$\endgroup\$
    – oabdullae
    Sep 4 at 15:58
  • \$\begingroup\$ @thebusybee A conditional jump predicated on an AND of masked condition codes is pretty useless... \$\endgroup\$
    – Kuba hasn't forgotten Monica
    Sep 4 at 18:29

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