I have a high-side switch using a PMBT2222A NPN SOT23 and MMBT2907 PNP. Now my concern is if my configuration not beyond the specifications of the PNP transistor like not going out of their max operating values at its base, even though I'm only about drawing small 15-20 mA on the PNP output and turning the transistors hard. enter image description here

  • \$\begingroup\$ Thank you, guys. I updated the question \$\endgroup\$
    – Citi
    Commented Sep 3, 2023 at 8:24
  • \$\begingroup\$ You also need to specify the max frequency for which you expect this to operate well and the source resistance/impedance of what's driving this (or information on its compliance current capability.) It really does matter a lot. If you want very high frequency response, then some care is needed. If the compliance current is low, then some care is also needed. Etc. More details = better. But given your output current, I'm guessing an LED for visual purposes and therefore the frequency is likely relatively low. But I'd like to know, for sure. \$\endgroup\$ Commented Sep 3, 2023 at 23:26

2 Answers 2


Presumably this is what you meant to draw:


simulate this circuit – Schematic created using CircuitLab

I am assuming:

  1. The signal at IN is a potential, either 0V or +5V
  2. The input won't be switching between those values faster than a few tens of kilohertz
  3. The load has negligible capacitance or inductance

If those assumptions are correct, this circuit will work fine, and all components will be operating "within specification". In fact, with the component values shown, you should be able operate a load of up to about 500mA 150mA [Edit: I don't know why I typed 500mA before, that was a brain fart] without issues.

  • 1
    \$\begingroup\$ With R1 1.2 k / Q2 base current ~7 mA I assume an output current up to 150-200 mA "safely saturated"; for 500 mA (too much for SOT 23 continuously), I'd be comfortable R1 160 (150) Ω, R3 not much more than 25 times that (5.1 k close already). \$\endgroup\$
    – greybeard
    Commented Sep 3, 2023 at 8:48
  • \$\begingroup\$ As Q2 passes through the point where it dissipates the max power it’s passing 10mA and dropping 4.5V, so dissipating 450mW which is more than the 350mW continuous rating. You might get away with it but would be better to use a transistor with a higher power rating. \$\endgroup\$
    – Frog
    Commented Sep 3, 2023 at 9:16
  • \$\begingroup\$ @greybeard Yes, I had a senior moment writing 500mA. Thanks for pointing that out. \$\endgroup\$ Commented Sep 3, 2023 at 10:20
  • \$\begingroup\$ Thank you ,@SimonFitch, greybeard, frog. Yes my main worry was that ~7ma base current on the PNP, On the long run. Im Not sure on the datasheet max Ib and beta with the load drawing small current 15-20ma. \$\endgroup\$
    – Citi
    Commented Sep 3, 2023 at 18:30

There are several topologies I try to keep in mind when using a different and higher output voltage than is being applied by an I/O pin or some other source:


simulate this circuit – Schematic created using CircuitLab

Since you haven't specified frequency of operation or the control line's compliance current and/or source impedance, I've provided the options I can quickly cobble out.

Only the upper-left and lower-right have fast turn-off times. And the upper-left is inverting in the sense that the load is powered when the input is low.

For low speed circuits all the above options are both fine. But the upper-right and lower-left choices have problems due to the "base charge storage reverse transit time" (model parameter is TR) for the output BJT. Since those times are nearing a microsecond for common junk-box small signal BJTs, this puts the turn-off time into the few-microsecond region. The lower-right adds a kind of bootstrap cap and uses a separate BJT to create an active pull-up to compensate this reverse transit time.

None of the above are two-quadrant outputs. So only single-ended loads.


Per Tim's comments below, I have tried to use LTspice's simulation to capture some interesting modifications and their results:

enter image description here

His suggestion for a cap across the emitter resistor is excellent. It certainly does help the leading edge! I also stiffened up the pullup to his suggested \$1.2\:\text{k}\Omega\$. It has so little of an impact that the added emitter capacitor actually appears to added about \$30\:\text{ns}\$ delay to the falling edge (while definitely improving the rising edge.)

This is just a simulation and there's more to discuss about it. But it is where I'm at, for now. Until Tim adds more commentary to help clarify.

  • \$\begingroup\$ A note on storage -- with judicious choice of R_BE (R2 here) and h_FE(sat), general-purpose transistors can go quite fast. Consider choosing a relatively high h_FE(sat), say 1/2 to 1/4 the linear (h_FE) value, and choose the resistor to draw the same base current. So the driver (Q2) supplies twice the base current. A 2N3904/6 switching 10mA in 20ns or so is typical this way. You'll only see whole microseconds for very weak turn-off (I(R2) < Ib/10, say?). \$\endgroup\$ Commented Sep 4, 2023 at 2:13
  • \$\begingroup\$ @TimWilliams I'll do some simulations to see. The one in the lower-right quadrant of the examples, turns off in about 10 ns (20 mA load) as shown. (Turn on is still slowish -- 100 ns or so.) I'll see if I can get there with what you are suggesting. Worth checking out! Thanks. I also should consider some kind of cascoded BJT if there's enough headroom for the idea. But without knowing what Vpos is, I'm not sure it's worth adding to the mix. \$\endgroup\$ Commented Sep 4, 2023 at 3:13
  • \$\begingroup\$ @TimWilliams I should add that I have in the past tried setting the R2 resistor to what I had imagined as being fairly stiff values. No real good from it. So I just tried what I think you were saying (the collector current for Q2 is twice what's needed for the base current of Q1 and R2 is set so small that it soaks up the rest.) I'm still seeing almost 500 ns delay on the falling edge. (2N3906 for Q1.) That's better than the earlier 2 us, of course. But..... it's not 10 ns. Not even close. (I can post what I'm playing with if you become interested enough to make your example more concrete.) \$\endgroup\$ Commented Sep 4, 2023 at 3:30
  • \$\begingroup\$ Sure, to be more concrete: bottom-left; IO = 0/5V (t_r < 10ns), R3 = 0, R1 = 4.7k, Vpos = 12V, R2 = 1.2k, RL = 680. Optionally 22-47p in parallel with R1. If you're still seeing slow edges or delays... maybe you don't have 2N390x's? :) \$\endgroup\$ Commented Sep 4, 2023 at 5:04
  • \$\begingroup\$ @TimWilliams Just LTspice sims. Here's the schematic + results. \$\endgroup\$ Commented Sep 4, 2023 at 9:39

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