Given this circuit I’m asked to determine the transfer function from $$\V_i\$$ to $$\V_o\$$, but there are no answers given and my result disagrees with my earlier DC analysis.

I think think the first “stage” is just a voltage follower. By superposition, it’s easy to show that $$\V_o’ = V_i\$$ (though I'm unsure whether I'm allowed to split $$\V_i\$$ like that):

simulate this circuit – Schematic created using CircuitLab

## For the second stage

simulate this circuit

Since $$\A_2\$$ is ideal, there is no current through $$\C_2 \parallel R_5\$$ so $$\0V\$$ drop across it, and the inverting port follows the non-inverting one, thus there is $$\-V_i\$$ across $$\R_3\$$, and by Ohm's law $$\i = -\frac{V_i}{R_3}\$$ running through it.

After which I did KVL (red arrows): $$V_o + i(R_4 \parallel C_3) + V_i = 0\\ V_o -\frac{V_i}{R_3}(R_4 \parallel C_3) + V_i = 0\\ V_o + V_i[1 - \frac{1}{R_3}(R_4 \parallel C_3)] = 0\\ V_o = - V_i[1 - \frac{1}{R_3}(R_4 \parallel C_3)]\\ \frac{V_o}{V_i} = H(s) = \frac{1}{R_3}(R_4 \parallel C_3) - 1\\ H(s) = \frac{1}{R_3} \frac{\frac{R_4}{sC_3}}{R_4 + \frac{1}{sC_3}} - 1 = \frac{1}{R_3} \frac{R_4}{sR_4C_3 + 1} - 1\\ H(s) = \frac{R_4 - sR_3R_4C_3 - R_3}{sR_3R_4C_3 + R_3}\\ H(0) = \frac{R_4 - R_3}{R_3}\\$$

However, I've found earlier through DC analysis ($$\R_1, R_2, (C_2 \parallel R_5)\$$ are short, $$\C_3, C_1\$$ are open) that the DC-gain should be $$\1 + \frac{R_4}{R_3}\$$.

I'm not even sure where to look to find my mistake.

• Are you certain that $i=-\frac{V_i}{R_3}$. Also check the polarities for KVL voltages. Commented Sep 3, 2023 at 17:18
• Aha, spotted it, it's the very first line in the KVL, it's supposed to be - V_i. I'm not sure what the correct procedure here is, should I answer it myself and pick that answer? Commented Sep 3, 2023 at 21:00
• @Learath2 Yes, just write your own answer and select it. Are you supposed to account for input bias currents? Speed-up C2, as well? Commented Sep 3, 2023 at 23:08
• I see. Ideal op-amps so no input bias currents. What do you mean by "Speed-up C2"? Commented Sep 4, 2023 at 12:33

The first line doing the KVL was wrong, leading to the wrong result. It's supposed to be $$V_o + i(R_4 \parallel C_3) - V_i = 0$$

If opamps are ideal, R1, R2, R5 play no role.

A1 is a buffer indeed. Note that due to virtual ground, no current flows through R6, and thus none through R7. So vin is buffered to vout.

A2 is a non-inverting stage, with gain G2 = 1 + R4/R3 = 1 + 27/9 = 4.

So, the TF(0) = 1 * 4. Which agrees with what you found before.

• We seem to agree that the DC-Gain should be 4, but at the very end I find H(0) = 2, so I must have made a mistake somewhere. Commented Sep 3, 2023 at 20:51
• Does the first-stage buffer have any practical use (compared to the "standard" op amp buffer) or is it just an academic problem?
– Hyp
Commented Sep 4, 2023 at 10:53
• @Hyp I'm not completely sure as I'm just learning these right now, but C1 makes this a Miller Integrator (a less than perfect one due to R7). So it does change the frequency response, though not sure what one might use it for :D Commented Sep 4, 2023 at 12:36
• @Hyp: some resistors may be employed for bias currents comepensations, which are not mentioned here though. So I'd say they're just there to test your knowledge.
– edmz
Commented Sep 4, 2023 at 17:27
• @Learath2: that's not an integrator. Input current is not being integrated.
– edmz
Commented Sep 4, 2023 at 17:28