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I mostly do VHDL/Verilog, and I'm laying out a PCB for a small FPGA project.

The FPGA will operate in a noisy environment. I want to make sure the board has more than enough capacitors to provide the FPGA with very smooth DC.

In this context, an acquaintance who does PCB layout told me, "Too much capacitance can hurt you." When I asked why, he was not able to give me much of a reason.

I'm trying to understand here. Aside from the board taking a few ms longer to reach its normal operating voltage, what downsides are there, if any?

Is there a reason that my friend wasn't able to communicate? Or is this idea nonsense?

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    \$\begingroup\$ If different capacitors of different values are combined together without careful planning, there's a risk of creating multiple resonance frequencies that amplifies rather than decreases noise voltage, as they create impedance peaks in the power delivery network, see Optimizing Power Distribution Networks for Flat Impedance, Heidi Barnes, Signal Integrity Journal. However, if PDN impedance has already been checked via simulation during design, I don't see any fundamental problem. \$\endgroup\$ Commented Sep 5, 2023 at 16:51
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    \$\begingroup\$ The fpga live too long after power off. It is hard to place many caps near Vcc pins. \$\endgroup\$ Commented Sep 5, 2023 at 16:51
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    \$\begingroup\$ As always start with what: how "very smooth" are we talking? Do you have exceptional jitter requirements here? Jitter I think is the only motivation for low supply ripple, until the whole system becomes ill-behaved from excessive (say >10%?) ripple. As for noise -- where is the noise coming from? How is it reaching the board/FPGA? Why isn't it filtered out or shielded away? These are the questions you must be asking. \$\endgroup\$ Commented Sep 5, 2023 at 17:08
  • \$\begingroup\$ @TimWilliams there is a large inductive load nearby. I will do my best to shield the PCB with mu metal, but that shielding is expensive and heavy, therefore it would be naive to assume the shielding can be as perfect as I would like. Mostly I'm concerned about board traces being inductively coupled to that large inductor and introducing noise into the PCB. \$\endgroup\$ Commented Sep 6, 2023 at 13:02
  • \$\begingroup\$ Is it though? -- the whole point of mu-metal is it's cheaper and/or lighter (for some practical/economic tradeoff between those two) than anything else; if it weren't, it wouldn't be used. Maybe the shield you're looking at is grossly mismatched to the application. (But how much magnetic field can the board handle, anyway? -- how much is reaching the board? It all comes back :) ) \$\endgroup\$ Commented Sep 6, 2023 at 13:09

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There are a few reasons you want to be careful about overdoing the capacitor decoupling.

Too many caps and subsequent layout compromises may increase the input inductance.

Too much capacitance may lead to large inrush currents that will cause problems with the regulators feeding the circuit.

I've even seen ringing-like effects on the rails that were hard to troubleshoot.

There are serious diminishing returns to using capacitance at your DC inputs, so the value of added more than needed is low, while the risk of introducing other problems begins to rise.

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In addition, "too much capacitance" may invalidate the start-up requirements of the FPGA.

Many FPGAs require certain lines to go "high" in a certain order, and within a certain timeframe. Invalidating this (by using too much capacitance) can cause the FPGA to reset, freeze, or otherwise misbehave in unpredictable ways. Every FPGA is different, so check the datasheet of yours carefully.

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The main problems with too much capacitance are:

  • Overloading regulators if they have a maximum output capacitance limit
  • Affecting the stability of regulators that have an external compensation circuit
  • Not meeting the minimum voltage ramp rate requirements of components (if they have any)
  • Increased inrush current (can cause voltage spikes with poor regulators)
  • Increased cost
  • Increased board area
  • More components means more points of failure
  • Possibility of resonance (quite rare, but can happen even with small amount of capacitance)

How much capacitance is enough?

Many manufacturers provide guidelines in datasheets, commonly "100 nF per supply pin, 10 µF per board". You can also look at their reference design boards to see what is used. These guidelines are usually way higher than the absolute minimum that would be needed for the design to work reliably, precisely because there is little harm in excess capacitance.

Power rail stability can be checked with an oscilloscope: use AC input mode and high vertical resolution (10 mV/div). Avoid long ground leads; instead use a ground spring. Digital circuits are usually fine with up to 10% ripple, though I'd aim for below 1% of the supply voltage.

If you are worried, you can always add a few more capacitor locations on the PCB that you will solder in the prototype if needed.

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