Does turn-on and turn-off delay cause MOSFET switching loss?

Question

I know during rise time and fall time, there are MOSFET switching losses.

Is same the case with turn on and turn off delay?

I don't see any relevant pics in internet with the IDS waveform included. Hence not able to figure out whether these delays cause any effective loss in MOSFET.

Image link.

Answer 1

As per this doc, there are no switching losses during delay time, but it can cause gate driver losses.

Answer 2

No, it doesn't, and you can see in the diagram the phase difference between the voltage rising on the gate and vds, the losses you have on a transistor are the rising and falling edges where you are on the ohmic zone for a brief time and the conduction losses due to the resistance of the transistor while fully open, the driver losses are due to gate capacitance

Answer 3

Yes, but not in a useful way.

Two basic reasons:

1. Loss is not, in general, proportional to these delays.

   I assume you were thinking, let's take the triangular power dissipation waveform between I rise and V fall, and call that switching energy -- and wondered if there might be something about the other times too. I see that -- it's a good suspicion. Alas, it doesn't work out.

   Actually, that method itself doesn't work out, which should be evident below, or I'll get around to explaining it.

2. There's switching loss in and around the event regardless, so, there being nonzero loss during these intervals, needn't really mean anything overall -- maybe it's a small percentage difference, a measurement error.

   The better question to ask, then, is: is there significant loss here, in relation to the overall switching waveform? And, again, the answer is: yes, maybe, it depends.

---

First, a few comments about the timing diagram: it's just that, a diagram. The relative timing of edges and 10/90% thresholds is arbitrary, shown only to label the respective intervals. It could equally well be that drain current flows for V_GS < 10% and we get an apparent negative turn-on delay! This doesn't violate laws of causality in any way at all, it's simply a matter of definition -- poorly chosen definitions perhaps, but that's why we must not be too picky about such a simplified diagram, and more careful about what the actual conditions are.

In particular, the edges might or might not overlap, which is of paramount importance to the reactances in the circuit.

Here, I've modified the diagram to show things a little more realistically. I haven't changed the gate-rise timing, but just imagine it may overlap.

Assuming V_GS is instantaneous (i.e., what we see at the pin is representative of what's on the transistor die itself), we see V_DS initially high and V_GS rise, so I_D must also rise. This needn't yield an external current yet: first the drain self-capacitance must be discharged, for V_DS to change, and only later does current flow through the resistor -- the test in question has a resistive load. (Other tests are done with constant-current or inductive loads, and may include a diode which causes hard-switching; check carefully for which type of test is being performed!) Thus, it can be that drain current (internally) rises quite a bit over the steady-state value, drawn as a dotted hump here.

Eventually, V_DS falls, load current rises (again, resistor: load current goes as (V_DD - V_DS) / R_L), and V_DS settles into the resistive region. But even as voltage seems to have settled (below the 90% mark, say), current can still flow: C_oss varies widely with V_DS, and in particular can vary an extraordinary amount with some types, like Superjunction MOSFETs (which constitute almost all commonly available types above 300V or so) can have a ratio of C_oss(0) / C_oss(V_DS(max)) over 100!

Now, during turn-on, R_DS(on) is just so low that it will tend to short out C_oss anyway (there are still internal charge-distribution effects in SJ types which take a little time to settle), but at turn-off, no such current excess is available, only I_D driving the voltage up. And since capacitance at low V_DS can be so extraordinary, this phase can take quite some time. In the process, drain current isn't really flowing -- I_D is long since zeroed -- yet power nonetheless flows into the transistor. What's going on here? It's charging C_oss, which takes energy, that's fine; but recall at turn-on, no complementary phase (capacitor discharge) occurred: energy goes into the superjunction, charging it, but it's discharged by the hard-switching turn-on, which costs turn-on energy.

So, this is one possible mechanism for energy to be lost during the delays, or around switching in general, that isn't simply the triangular waveforms commonly diagrammed -- which depends on how you're using the transistor, what the surrounding circuit and load are like, etc.

As it happens, the SJ energy loss effect is like a simple R+C in parallel with the transistor, so it has little loss at slow rates of change (100s ns, say), but incurs "full" switching loss when commutated rapidly (10s ns). Note this occurs regardless of "who" is doing the switching: you can strap such a MOSFET with gate to source, so it remains perfectly off, and run its V_DS up and down and measure this loss mechanism independently.

---

For other types, again, it depends. The C_oss ratio is large, easily more than 5, but there isn't necessarily loss associated with it (or at least as much as SJ). In hard switching turn-on, C_oss energy (E_oss) is simply dissipated, no way about it; in ZVS resonant applications, this energy can be "stirred" with the load reactance, which requires a synchronized dance of proper switching/timing (but, as it happens, isn't terribly complicated, it largely reduces to variable-frequency drive), and obviously a specialized output network and other considerations, but this is, in short, why resonant converters are popular for compact, high efficiency power supplies.

As for the triangle diagrams -- they are just that, diagrams. You'll see figures like this:

^{From: https://www.everythingpe.com/community/what-are-switching-losses-in-a-transistor}

and, as we've now covered, all these slopes have weird curves to them instead -- I_D(V_GS) is a parabola (more or less), V_DS drops sharply at high voltage, slowly at low -- and there can be other knock-on effects like the SJ internal resistance effect discussed above. In general, the power waveform will not be triangular, and this figure is at best a basic starting point; it is far from the final truth.