I'm trying to design a 555 circuit that outputs a low frequency PWM signal (1-10 Hz) and is adjustable in both frequency and duty cycle (0-100%). I've come across this design and it seems to work pretty well assuming I use two potentiometers for the resistors. Basically the output time(sec) values Ton and Toff are adjusted using the below equations:

Ton = .67 * R1 * C

Toff = .67 * R2 * C

Ton = Duty/Freq

Toff = (1-Duty)/Freq

When I've been simulating this (shown below) I'm finding that the actual duty cycle and frequency have some error compared to the "calculated" values. How can I account for this difference between calculated and actual?

555 PWM circuit simulation

***Update to illustrate the error further, to get to 1Hz 50% duty i needed to adjust the values to the below. Right now i just "guess and checked" but would like to understand it better and be able to have equations that more accurately describe this behavior. enter image description here

  • \$\begingroup\$ How much error is "some error"? What is the tolerance on the values of your timing resistors & capacitor? \$\endgroup\$
    – brhans
    Sep 6 at 15:51
  • \$\begingroup\$ Like in this simulation for example, the calculated values for a 1Hz 50% are R1=R2=7463ohm. In the scope shown its outputting .88Hz at 54%duty. I haven't built this circuit outside of this simulation yet so resistor tolerance shouldn't be an issue. Other combinations are off similarly. \$\endgroup\$
    – bdmcnamara
    Sep 6 at 15:55
  • 2
    \$\begingroup\$ The diode in series with R1 introduces some error. \$\endgroup\$
    – Jens
    Sep 6 at 15:56
  • \$\begingroup\$ Yeah i figured that the diode was causing the error, i guess i'm trying to figure out how to calculate that so i can account for it in my equations. The diode is needed to be able to get the 0-50% range of the duty cycle. \$\endgroup\$
    – bdmcnamara
    Sep 6 at 16:10

2 Answers 2


Yeah i figured that the diode was causing the error, i guess i'm trying to figure out how to calculate that so i can account for it in my equations.

The equations you cite are simplifications of the actual equations for capacitor charging and discharging. You need those equations. Why? Because with the diode in there, the 555's internal reference divider and the external R-C circuit no longer have the same operating voltage.

During the positive half-cycle, when the cap is charging through the R1, the peak voltage that is charging the cap is reduced by the diode. Subtract the diode's Vf from Vcc in the original charge equation to correct most of the error.

Another error source is the charging current through R2. Even though the voltage across R2 is clamped at the diode's Vf, there still is a small current through R2, determined by Ohm's Law.

There is another form of the astable circuit that might work better for you. It is in the datasheet for the CMOS 555, such as the LMC555. The circuit has the timing capacitor charged and discharged by the output. With a single timing resistor, a near perfect 50/50 waveform pops out. Here is an example from another site. Replace the one R4 with two pots and two diodes (one pointed each way), and you now have completely independent charge and discharge adjustments.

enter image description here


  • \$\begingroup\$ That makes a lot of sense, thank you for sharing that! Do you have any resources for how to calculate the charge/discharge times? \$\endgroup\$
    – bdmcnamara
    Sep 6 at 19:50

Adding components like diodes makes it much harder to accurately compute the timing of a 555 circuit, since it will be very sensitive to variations in precise diode characteristics. A variation on the 555 astable circuit which allows balancing the duty cycle without using non-linear components such as diodes, and doesn't rely upon the 555's output swinging all the way up to the supply rail (which it doesn't), is to add a resistor from the capacitor/inputs node directly to VDD. Without that resistor, the charge time would be longer than the discharge time, but adding that resistor will increase the discharge time while reducing the charge time. For a minimal duty cycle boost, the extra resistor should be quite large. I think a discharge resistor of 1K, a "normal" charge resistor of 10K, and an "extra boost" resistor of 316k should yield a duty cycle very close to 50%.


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