I was having a discussion with a colleague at work regarding derating of MLCC capacitors when used as a DC block capacitor. My colleague mentioned that it is standard practice to derate MLCCs with the applied DC voltage. This means we are using 1kV capacitors of C0G dielectric as DC block capacitors that only experience a voltage of approximately 100V.

Now, I am fully aware of the DC voltage derating requirements of X7R capacitors and similar dielectrics, but I was under the impression that one would not need to take such measures with C0G dielectrics which do not suffer from such effects.

I had suggested the use of 200V C0G MLCCs which we could use to achieve an equivalent amount of capacitance in a substantially smaller solution size. I did not understand the reason to use such high voltage, large capacitors. These are stacked capacitors and are fairly bulky, with multiple capacitors stacked on top of each other, acting effectively in parallel.

What is everyone else’s experience regarding the use of C0G capacitors as DC blocks? The H-bridge inverter voltage is around 400VDC so I have since been thinking it may be something to do with that. Is there any other reason to use such high voltage rating MLCCs if you are utilising C0G dielectric? I would even assume using X7R at 50% of the rates voltage and approximately doubling the total capacitance would be fine for a simple DC block application.

  • \$\begingroup\$ what kind of load? If it is inductive: are flyback or similiar in place? What is the requirement for ESR? What is the expected power dissipation? \$\endgroup\$ Sep 6, 2023 at 18:00
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    \$\begingroup\$ Do you mean derating for capacitance change with DC bias? Usually just picking a higher voltage rating capacitor will not help, you need to go to a larger package or better dielectric, even at the same voltage rating. \$\endgroup\$ Sep 6, 2023 at 18:00
  • \$\begingroup\$ The H-bridge drives an inductive resonant tank and transformer but the load is purely capacitive. ESR has to be as low as possible as does the power dissipation, which yes points towards using a larger package size, but the reasoning given was due to MLCC being poor with applied D.C. volts. Picking a higher voltage rated MLCC without changing package size, assuming the % change of the X7R doesn’t change, should mean that the effective capacitance is higher. Choosing a 1kV X7R and operating it at 100V, for example, would make sense - but not a C0G. \$\endgroup\$
    – jvnlendm
    Sep 6, 2023 at 18:38
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    \$\begingroup\$ Remember to consider also creepage distance, smaller SMD packages may have the terminals too close together to comply with standards without conformal coating. \$\endgroup\$
    – jpa
    Sep 7, 2023 at 6:09

4 Answers 4


There are two significant misconceptions from your colleague:

  1. Type 2 dielectrics, in general, need voltage derating, or some [fixed] ratio thereof.
  2. All ceramic capacitors, in general, need derating.

The underlying reasons I can only guess at, of course, but my guess would be they erroneously generalized #2 from #1: that is, applying the same principle, without understanding the reasons why #1 is done (or isn't) in the first place.

The reasoning behind #1, in turn, is not stated (and doesn't really matter here), so it may be that it is done correctly -- but it may also be that it is done erroneously as well. I've seen this more than a few times myself, so it seems worth discussing again.

Type 2 dielectrics exhibit nonlinearity, that is, capacitance varies with applied voltage. It also varies quite strongly with temperature. The type code describes the temperature characteristic. Voltage dependence is not defined by any standard (at least, that I know of, or at least not these tempco standards), and is up to the manufacturer to represent, and the user to select.

To emphasize: voltage rating does not determine electrical characteristics.

You can equally well find a 1uF 50V X7R 0805 that is -90% capacitance at rated voltage, or -70%. (You probably won't find one that's -30%; though I don't recall offhand what the highest I've seen is.) Not to mention, the height of the chip can vary, and further still, the amount of active material -- the manufacturer is free to put electrodes throughout the full stack height of the chip, or just a few in the middle, as long as it meets breakdown voltage ratings at a high enough yield to be economical to sell.

The takeaway from all this is, an electrically large chip, for its volume, is likely to be a tall (e.g. height = width) chip, that fills the whole volume with electrodes; but is also likely to have a substantial C(V) effect, i.e. C(Vmax) maybe -90% of C(0). Smaller values, in a given chip size, can have fuller C(V) curves (more valued retained under bias), but can also be made the "cheap" way, and you have no way of knowing short of measuring the thing.

What does this mean for derating?

In general, we cannot pick some fixed ratio. There are tons of capacitors that are perfectly serviceable at rated voltage. Most 6.3V chips I've seen are this way; at least at modest values like 10uF 0805. Conversely, I've seen "1uF" 250V X7R 2220s that are close to -95% at rated.

Perhaps they simply can't make layers thin enough to break down at very low voltages -- we're talking 100s nm layer thickness here, and ~thousands cm2, so a manufacturing defect (pinhole, crack, etc.) is far more likely than avalanche breakdown, and corresponding C(V) reduction while approaching it. Which is probably also why the C(V) / C(0) can be so much worse at high voltages.

What should we do, then?

The only thing we can do, is set an acceptable lower limit (for which we should also include basic value tolerance, change with temperature, and aging effect), find the corresponding point on the C(V) curve, and keep shopping until we find acceptable parts.

Tedious, yes -- I often take ten or twenty minutes to select a new capacitor by this process. It's unfortunate that manufacturers don't provide tools to search their parts automatically, but it's rare enough they provide such data at all.

As for C0G and other type 1 dielectrics -- they do not exhibit a C(V) dependence, so can be used at (or indeed perhaps beyond*) ratings, with no derating.

Other Limits

Mind that physical limitations may apply, for example an 0805 capacitor might be available up to 1kV, but it sure as hell ain't gonna count for 1kV as, say, "basic" insulation; functional at best, but even then it may have to be potted for reliable operation. (On that note, being ceramic material, they do have good CTI for insulation purposes; trouble is, one face is always in contact with a poor-CTI circuit board...) So, mind realistic voltage ratings, and choose body size/type accordingly. There are 1808 size chips for this purpose, for example.

Or, for risk items like cracking, where you might want to use series parts in case one can fail shorted -- obviously, the remaining part needs to handle the full voltage, even though the series pair nominally handles double the voltage. Cracking can be mitigated with choice of termination material, or by managing the mechanical design more closely (more rigid assembly, keep capacitors away from flex points).


*At your own risk, of course.

Whether transient (or continuous, for that matter) overvoltage is acceptable in a design, is a different matter. If you need to compromise reliability to trade for cost, space, etc., overvoltage may be an option. You'll most likely want to work closely with the manufacturer(s) to determine what likely failure and aging statistics are, and so, how much voltage is acceptable in your application.

Note that ceramics don't fail incrementally, like self-healing film capacitors do. They fail shorted, one and done. So, first of all, your risk curve is a lot steeper to use ceramics this way.

Overvoltage can be used responsibly. Famously, compact fluorescent lamps (CFLs) operate with a starting capacitor, that sinks a large current through the lamp filaments to heat them up and begin conduction (thermionic emission), in the process developing a substantial voltage. A (physically) small capacitor is used to save cost: these types actually provide failure statistics in the datasheet. They are chosen so that, on average, they fail (value decreases below operational tolerance) about as often as the tube itself does. (Well, probably not exactly, but in the ballpark.) These are well engineered devices -- or at least, they can be, where "well" includes exploring these darker, statistically motivated sides of engineering!

Note that parts are tested to some overvoltage during production (in a suitable method, lot sampling or total). Real parts may break down at several times rated voltage -- how many, you just don't know, of course. I've heard of 16V X7Rs handling anywhere from 30 to 120V, for example.

In contrast, self-healing film capacitors don't fail shorted (or at least, are unlikely to), but as the name suggests, they evaporate the affected region and continue at reduced ratings (ESR goes up and C goes down). The change is tiny at first, but as healing events stack up, eventually whole sections of electrode become weakly connected or broken entirely, and ESR and C diverge rapidly. This progressive failure mode is well suited to EMI filters (exposed to occasional mains surge), and CFLs (startup cycles are ultimately limited by the lamp itself), hence their selection.

Also, pay attention to the difference between AC RMS (if given) and DC ratings. Usually the DC rating is closer to the peak-to-peak rating. Some manufacturers specify conditions for converting between these; usually DC is the same as AC + bias (no zero crossing), i.e. the peak voltage matters; and AC (zero crossings, or no DC) counts extra (use p-p voltage). Additional derating may apply, and, of course, check current or power ratings, or maximum AC/ripple.

  • \$\begingroup\$ Thank you for such a complete and thought through answer, Tim. I’ll certainly have to bring this topic back up tomorrow to clarify. I have also certainly found it strange when manufacturers market a 250VDC capacitor as 1uF considering the Derating effects. I have used SimSurfing from Murata before which can prove quite useful at visualising these effects in their products, but I know of no other manufacturer that does anything similar. \$\endgroup\$
    – jvnlendm
    Sep 6, 2023 at 18:52
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    \$\begingroup\$ Several have such data, just not usually in the datasheets; TDK, KEMET, Taiyo Yuden and Samsung come to mind, and a few others. \$\endgroup\$ Sep 6, 2023 at 18:54
  • \$\begingroup\$ Your answer starts off saying there are 2 misconceptions. But 1. isn't a misconception, the next paragraph say it's true, something that's done in practice. If I understand correctly, there's one misconception (2.) which resulted from an incorrect generalization from 1. The presentation is also not good for skimming. If you wanted to do keep the list, it might be good to put 1. foo (true) 2. bar (false) so people skimming can instantly see which list item is correct and which isn't, even if you do fix up the surrounding text to not call them both misconceptions. \$\endgroup\$ Sep 7, 2023 at 9:48
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    \$\begingroup\$ One of the downsides of stream-of-consciousness writing, @PeterCordes. Recommendations and edits are welcome! || ...Hm, there; found a lot of low-hanging fruit today, that should make things a little easier. \$\endgroup\$ Sep 7, 2023 at 13:05
  • \$\begingroup\$ Some capacitors in very small packages can have extremely high C(V) dependence - I've used 0201 or 01005 packaged components where the capacitance was down to 10% of marked value at rated voltage (which was only 4V or so. \$\endgroup\$ Sep 7, 2023 at 13:57

Murata says in their ceramic cap FAQ that C0G caps have no DC bias characteristics.

So either the caps need to be derated for other reasons, but at least they don't need derating due to capacitance changing with voltage.

  • \$\begingroup\$ I’ll have to have another conversation tomorrow to see I’ve missed anything, but this was my suspicion. The reasoning was to do with MLCC not dealing well with applied DC volts which is what confused me. \$\endgroup\$
    – jvnlendm
    Sep 6, 2023 at 18:39

C0G and in general class 1 dielectric ceramic capacitors don't derate neither with temperature not bias voltage, class 2 on the other hand do, the lower the number of that dielectric the higher the derating (X5R behaves way less ideally than X8R)

here you have a nice intro to this


  • \$\begingroup\$ C0G/NP0 do not need derating due to DC voltage. Neither is the losses much in a C0G compared to NP0. \$\endgroup\$
    – user103776
    Sep 7, 2023 at 14:27

C0G/NP0 do not need derating due to voltage. C0G compared against other MLCC like the X7R, do barely dissipate any energy in AC mode in comparision.

I've used C0G in 1000V boost converter to snub the low side switch. I did not need to have a factor 10x over the 1000V, so you are right and your colleagues probably do not understand the difference between diffrent MLCC well enoughe. A 200V rated cap should be fine if the maxiumm voltage is not over 100V, however is high spikes/esd event present you may want to consider higher to have a margine but that is not due to derating.

  • \$\begingroup\$ Low loss is an understatement; they're just about as ideal as you can get in a capacitor! Paralleling them can even be a little annoying, as the Q factor of the resonant modes within the set can be relatively high (i.e., more than 1). \$\endgroup\$ Sep 7, 2023 at 18:19

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