2
\$\begingroup\$

I'm taking a course on CMOS circuit design and, from my course slides, I have that the the low-high propagation delay of a matched CMOS inverter is given by

$$ \frac{2\,L\,{\left(C_{\textrm{DB2}} +C_W +C_{\textrm{db1}} +2\,C_{\textrm{dg2}} +2\,C_{\textrm{gd1}} +L\,W_n +L\,W_p \right)}}{V_{\textrm{DD}} \,W_n \,{\left(\frac{{V_t }^2 }{{V_{\textrm{DD}} }^2 }-\frac{3\,V_t }{V_{\textrm{DD}} }+1.7500\right)}} $$

where the capacitances are as given in this diagram:

enter image description here

I'm trying to fully understand the theory of how to optimize for minimum inverter delay, so I started playing around with the equation in MatLab. Specifically, I did this:

 syms W_n W_p L V_DD V_t C_gd1 C_dg2 C_db1 C_DB2 C_W, assume(W_n > 0 & W_p > 0 & V_t > 0 & V_DD > 0)

% constraints on capacitance
C_int = 2*(C_gd1 + C_dg2) + C_db1 + C_DB2;
C_g3 = W_n*L;
C_g4 = W_p*L;
C_ext = C_W + C_g3 + C_g4;
C = C_int + C_ext;

alpha = 2/(7/4  - 3*V_t/V_DD + (V_t/V_DD)^2 );

% main equation
t_PLH = alpha*C/((W_n/L)*V_DD)
equation = simplify(diff(t_PLH, W_n))

and got this as the partial derivative: $$ -\frac{8\,L\,V_{\textrm{DD}} \,{\left(C_{\textrm{DB2}} +C_W +C_{\textrm{db1}} +2\,C_{\textrm{dg2}} +2\,C_{\textrm{gd1}} +L\,W_p \right)}}{{W_n }^2 \,{\left(7\,{V_{\textrm{DD}} }^2 -12\,V_{\textrm{DD}} \,V_t +4\,{V_t }^2 \right)}} $$

which doesn't have any zeroes, assuming the capacitances and length and widths are all positive (which, of course, they must be).

That seems to imply that, in principle, we could make the propagation delay arbitrarily small. However, my professor's slides also say that we can't make the channel width in particular arbitrarily small in order to decrease propagation delay, because doing so increases the capacitance, which increases the propagation delay, which seems to contradict the result of taking the derivative of \$t_{\text{PLH}}\$.

So what's the actual relationship here between propagation delay, capacitance, and channel width, for a CMOS inverter? What actually prevents the propagation delay from being made arbitrarily small?

\$\endgroup\$
3
  • 2
    \$\begingroup\$ A rule of thumb: in practice, the propagation delay is dominated by the loads and interconnects, so no matter how “fast” the transistor is, the delay is a strong function of feature size. Speed is determined in practice by how well you can optimize how logical effort is allocated to each mos device. The device sizes will be determined by logical effort. Optimizing for propagation time in vacuo will make everything slower, since logical effort drives performance (or rather lack thereof). \$\endgroup\$ Sep 8, 2023 at 14:06
  • \$\begingroup\$ The fundamental problem with your theoretical model is that your capacitors are fixed. That model fails to account for the fact that the capacitors are also a function of your W, L and bias conditions as well. \$\endgroup\$
    – Designalog
    Sep 11, 2023 at 9:35
  • \$\begingroup\$ @designalog, Is there another specific model I should be looking at instead? \$\endgroup\$ Sep 12, 2023 at 4:27

2 Answers 2

3
\$\begingroup\$

Intuitively, one can think of having a large W/L ratio (which is the only parameter you can modify as a designer) to increase the drive strength of the inverter. In that way, the CMOS inverter will be able to source or sink more current, thus driving the load more effectively.

However, this is a very limited view of the situation. Your (now huge) CMOS inverter will appear as bigger capacitance load to the preceding stage. Therefore, this preceding stage needs to spend more time driving your CMOS inverter. Unfortunately, ideal input voltage sources that can source or sink any amount of current do not exist.

Another limitation is that the bigger your CMOS inverter, the more its output parasitic capacitance will be. There is a point where this parasitic capacitance will actually dominate instead of the external capacitance load (e.g. another CMOS inverter) and you'll get diminishing returns (or worsening) on improving the propagation delay.

There exist expressions using the so-called "logical effort" to estimate delays and such. If I recall correctly, using smaller CMOS gates within a chain is best.

Another common technique explained in textbooks to increase VDD to decrease propagation delay. This works because now there's a larger VGS (or VSG for the PMOS) voltage hitting the CMOS inverter gate. If the input signal is 0, then the VSG will be larger if VDD has increased, as \$V_{SG}=V_S-V_G=V_{DD}-0V\$.

Why can't we increase the supply voltage indefinitely, then? integrated CMOS circuits have a maximum supply voltage before going outside their safe operating area regions, which are defined by your fab. In other words, if you were to increase the VDD indefinitely, the reliability of your circuit during operation (with such increased VDD) would be compromised.

In addition, you can imagine that a larger supply voltage means the CMOS inverted needs more time to drive its output to VDD or GND. The other more obvious disadvantage, is an increased current consumption and heat.

\$\endgroup\$
1
\$\begingroup\$

Making the channel width smaller doesn't increase the capacitance--it does, in fact, decrease it. However, it does increase the effect of the next stage's capacitance--a narrower channel means less drive strength, which means it can't supply as much current to charge those capacitances in the following stage.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.