I'm new to PCB design and I'm wondering if it makes sense in a two layer PCB to fill any free space on the top and bottom layer with a ground area.
In most cases large ground planes are a good practice to minimize EMI or to eliminate the need for running extra ground traces. However there can be special cases where you could run into problems with ground connection integrity or clearance issues for some components. Creating unintentional current loops or long single ended shapes could actually create EMI problems.
To insure you have good ground integrity it is a good idea to add a handful of vias that connect between the top and bottom ground planes. Look for any ground plane sections that may have reduced or restricted ground current paths, consider moving other components or traces to allow for wider ground paths, if needed add extra vias from top to bottom to improve the ground returns in those areas. One such area I see on your board is the ground plane under C1, C3, C4, C8, C9, the ground return path for that area is very restricted, widen the ground connections or add vias to connect the top and bottom ground planes within that area.
On your board consider that when sliding the coin battery under the mounting bracket you could be sliding the positive contact over copper that could potentially make a short circuit. While solder mask is usually a good insulator it can often be scratched or chipped to allow contact to the copper. With just a few battery removals and insertions you may start to wear down the solder mask layer. On your board it may be best to reduce the copper fill areas (and traces) running on the top layer where the batteries will be in direct contact or sliding over. You can use keep-out polygons to control where the ground copper planes flow.
Other places to keep ground connections wider or to use extra ground to ground vias would be near the ground pins of ICs, voltage regulators, and where ground signals are coming onto or going off the board.
If an unavoidable long trace tends to divide a ground plane into separate disconnected sections consider adding vias from top to bottom to stitch the ground plane back together.
Finally, there seems to be a few places on your design that could be improved. For example the long trace coming from R5 could be shortened by partially running it on the bottom layer then back to the top layer. This could also eliminate the need for several other signal vias that currently cross under that trace. Reducing the number of traces that need to flip between layers can improve the continuous ground plane shape on the other layer. The long traces from the battery contacts to the power switch are not ideal, if you were to redo this board it may be better to keep the batteries, power switch, and even the voltage regulator closer together. Near the voltage regulator, it may help to keep the input and output caps closer to the regulator pins (rotate and placed them lower nearer to the pins). If the regulator's center tab is being used as a bit of a heat sink that trace or pattern could be considerably larger in area to improve heat dissipation. Avoid making trace connections at less than 90 degrees, sharp trace corners can create manufacturing problems and even increase the potential for stress cracking.
Be sure to read through the other comments and answers for additional ideas for improvement.
Well, what would have been good advice for a 2-layer board is to use as little and as short tracks as possible on the bottom layer. So you have an as solid as possible reference plane.
As for filling top and bottom with ground the way the PCB is routed right now: No one can tell. It may make signal integrity worse or better. It may make EMC worse or better.
The only advantage I can image is for PCB production: Evenly distributed copper on the outer layers is usually advantageous for the plating process, because it helps ending up with uniform plating thickness on all areas of the PCB.
Years ago when I was etching my own boards, ground and power copper pours reduced the amount of etchant required, and time to completion. These were non-critical, simple boards. I have had mostly good results by just using logic power and GND on opposite sides, with extra care spent on sensitive analog and signal nets, and everything "just worked". Of course, years of prior experience were invaluable, along with examples of more "professional" designs. For first runs where you expect to do some cuts and jumpers, keep copper pours to a minimum with plenty of room for modifications. Fine tuning can be done later.
30 years ago PCB fabrication was an expensive process, and you would usually want to roll no more than two or three runs. Even small simple boards could be a couple hundred bucks. Now boards are essentially "free", and you just want to minimize design time and use simulation as much as possible. High frequency and concerns such as RF emissions and regulations require more of a balance between processes. It's often a strange new world when you deal with GHz clocks and microvolt potentials and nA leakage issues.
I'm new to PCB design and I'm wondering if it makes sense in a 2 layer PCB to fill any free space on the top and bottom layer with ground area.
You are starting your question from a bad place. You should minimize tracks on the non-component side first and then, use as much copper for ground on that layer as possible. In other words, make your design work with a single decent ground plane then, your question somewhat becomes relevant.
Move the batteries to the left of the MCU to free up routing space. Move the MCU and the top/bottom pin headers to the right, to keep those traces short and for ease of routing.
Start with nothing but ground plane on the bottom, and "components in an open space" on the top.
Route all signals on the top, with only short jumper traces on the bottom. Keep the ground plane as undisturbed as possible. No long traces cutting it into pieces!
At that point, there won't be much usable space for ground on top, and it wouldn't improve things by a lot.
It will help though to have a local VCC fill on the top layer under the MCU. The GND MCU pins should then have local vias going straight to the ground plane on the inside of the chip's outline. The VCC fill can then be brought out to a pin header using a single fat trace (20-30 mils wide).