I have a PWM signal going into an ADC.
After the ADC the signal is being filtered using an IIR single pole filter.
Performance is exactly what I want with one exception. The purpose of the filter is to average a voltage at the ADC that represents a current. For high duty cycles getting an estimation of the average current with the low pass filter is trivial. For low duty cycles the average can sometimes be zero or fluctuate too much, meaning the filter gives imprecise values at low duty cycles.
I would like to avoid this without too much complexity. Any ideas?
The frequency of the PWM being measured can be between 0 and 250Hz. I have DMA running the ADC values to a buffer, I'm not sure what the actual adc cycle rate is but the filter loop is 10kHz. The chip is running at 16Mhz while the ADC has a prescaler of 6, so the ADC clock rate should be 2.6MHz. I'm currently doing 12bit ADC but less is possible with 28 cycles per conversion.
Increasing the sample rate is one thing. I will do that but the issue in my mind relates to the rate at which the signal decays. For 90% of the signal period the filter will be averaging using the value zero as an input, regardless of what the sample rate is. I'm more concerned about this.