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Shielding vias are used around high speed digital and RF traces. The return current for these kinds of traces primarily flows through the adjacent reference/ground planes.

If blind/back-drilled vias are not an option for shielding vias, is it ok to have a stub on the shielding via formed by the portions of the via barrel above/below the reference planes?

I'm referring to signal frequencies at or above 32GHz.

via stub]

Shielding via

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  • \$\begingroup\$ I see two stubs much longer already (1cm?), per pair. Surely those are the priority? Presumably there is GND plane below this layer, so the GND via stubs aren't visible to the signals shown? Something tells me this board is not a 32GHz example. \$\endgroup\$ Sep 13, 2023 at 16:31
  • \$\begingroup\$ I didn't post my via/design. Those pictures are just stock images for visual aid. \$\endgroup\$
    – aghoras
    Sep 13, 2023 at 16:50

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I've done design work, supported by SI engineers, at up to 25 Gbps and never had a problem with stubs on stitching vias. As long as the vias are there to connect the layers they're supposed to connect, they are doing their job, and the stubs aren't preventing that.

The main issue with stubs on signal traces is that they produce a shunt capacitance from the signal line to either ground or some other unexpected circuit node. A stub on a stitching via doesn't do that, because it's already (notionally) at the ground potential.

That said, if you're working at 32 GHz then you should be doing EM simulation (HFSS/CST/...) as part of your design/verification process. If it shows you a problem with the stubs, don't ignore it. Any problem would likely appear as a significant current in the stub at certain frequencies (resonances of the stub structure).

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  • \$\begingroup\$ I'm definitely going to simulate this with CST but I'm working on the prelim stack up right now and was hoping for some hints as to what to expect. \$\endgroup\$
    – aghoras
    Sep 13, 2023 at 19:45

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