0
\$\begingroup\$

I need a bit of debugging help with SWT81200 PLL that I am using on my custom designed PCB. I am able to configure registers through SPI communication, but the problem is that I am not able to achieve locking the PLL. All the voltages of 5 internall LDOs seem to be correct.

Link to the PLL chip: https://eu.mouser.com/ProductDetail/STMicroelectronics/STW81200TR?qs=Ok1pvOkw6%2FqLvBx%252BVW43ZA%3D%3D

As a reference clock I am using a crystal oscillator on the link bellow: https://eu.mouser.com/ProductDetail/SiTime/SiT8209AI-21-33S-100.000000X?qs=sGAEpiMZZMukHu%252BjC5l7YbKzh8ugEIuM4%252BQSOxXc7e8%3D

I have tried to measure my single ended 100 MHz reference clock with my Siglent SDS1202X-E oscilloscope and I don't see the square kind of clock but more sinusoidal clock of 100 MHz. Could this be due to limited capabilities of my probes and oscilloscope? In datasheet of the PLL it is also stated that the REF_CLKP and REF_CLKN pins should be biased to DC operating point but I don't measure any voltage on the pins when I probe it. I am using the configuration of SPI registers as it is recommended in the datasheet on page 51. enter image description here

I am attaching bellow the schematics for my circuit. enter image description here

What would you recommend me to check again? I can provide here measurements I would just need someone a bit more experienced with PLLs to give me some guiding recommendations.

\$\endgroup\$
0

2 Answers 2

0
\$\begingroup\$

Did you see this ?

I don't see the square kind of clock but more sinusoidal clock of 100 MHz ...

For a signal of 100 MHz, a scope as the "sds1202x-e" should be a little "short" as bandwidth is "only" "100 MHz or 200 MHz", not precisely known (some error in the description text)? ...

So, what you see is "regular". The scope is a "little short".
Probes included, bandwidth should be at least 10x times the signal frequency.

\$\endgroup\$
0
\$\begingroup\$

The recommended clock configuration for a single ended input (A), shows an AC coupling capacitor in series on the REF_CLKP pin, allowing the DC bias to be set internally to the PLL. In your schematic this pin appears to be directly connected. Try with the recommended capacitor instead of R21.

The sine wave when observed with the scope, is because the scope bandwidth is attenuating out the higher frequencies that form the rising and falling edges of the square wave. You would need to use a higher bandwidth scope to see the clear edges.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.