I have read a lot of posts, forums, and application notes about why it's a bad idea to separate ground or power in mixed analog and digital circuits, so I've made a 4 layer PCB with full GND and VCC planes inside, and the signal routing outside.

One thing I can't elucidate is if it's a good idea to make a VCC plane at all. In some cases people say that having a GND and VCC planes separated by a dielectric acts as a decoupling capacitor, but some others say that maybe it's better to have 2 ground planes and route the power like another signal, with the correct width. In my particular case, it would be may be difficult to route all the power net in my PCB, but it's not impossible.

I'm asking for some advice about why yes, and why not, and if someone has experience with both designs tell me if there's any preference.

  • \$\begingroup\$ What makes sense depends on the needs of your circuit and wiring between the chips. We can't give any specfic advice without knowing what specific circuit you have. Like sensitive analog or high speed RF trasmission lines or high speed differetial buses or just plain SPI buses. \$\endgroup\$
    – Justme
    Commented Sep 14, 2023 at 16:57

5 Answers 5


Take a step back: Why do we choose 0V for the net of the plane in the first place?

  • Because very many components need to connect to it anyway and very many return currents flow through this node. So making it with traces - all tightly aligned with their corresponding forward current traces - would be rather involved or even messy. So we give up a little bit of freedom and instead decide that all of this node is simply dumped into L2, which makes routing the rest easy.

Now, the motivation for making another plane for power is the same:

  • If you have many components that must connect to (the same) power node and you plan on having a lot of signal return currents through that power node, making it a plane is sensible. However, as this power node should be also tightly coupled itself to 0V, a standard 4-layer stackup with a tall dielectric between L2 and L3 makes this pretty hard to satisfy. So this is typically something you would do in a 6-layer board or custom 4-layer stackup.

Why not to make power planes in regular 4-layer boards?

  • It will not be tightly coupled to Ground for standard stackups, which makes it bad for high frequencies anyway. Can just go with routed nets.
  • You try to keep HF currents local anyway, so the power net best carries only low frequencies, so why not route it?
  • for mixed-signal board, you tend to have many different power nodes, none of which is really needed everywhere.
  • 1
    \$\begingroup\$ "Tightly coupled" is a matter of opinion: a 1mm spacing, over the entire area of a board, gives a transmission line impedance of a few ohms (at frequencies where that's relevant; 100s MHz say). This might still not be adequate for the most powerful loads (say a large FPGA or CPU drawing dozens of amperes, peak), but in that case you need more layers anyway, so can have more plane pairs, which will be of closer spacing. \$\endgroup\$ Commented Sep 14, 2023 at 17:25
  • \$\begingroup\$ @TimWilliams yes the power supply impedance can be sorta low even with ~1mm spacing. But the issue with such a large gap is for signal integrity because a lot of power supply return currents will flow in the more tightly coupled signal traces, which can give rise to hard-to-anticipate reliability issues. \$\endgroup\$
    – tobalt
    Commented Sep 14, 2023 at 18:08
  • \$\begingroup\$ What's the significance of supply currents, anyway? If your argument isn't symmetrical, something is fishy: CMOS works equally well from VDD or VSS. (Well, not equally, but close enough for purposes.) Why should one be privileged over another? || I don't understand your claim about signal layers -- power supply currents don't return through traces that aren't there; and I don't see what that has to do with reliability (maybe current through ESD diodes, or breakdown? but signal quality would have to be downright atrocious for that to begin to matter; so I'm not sure). \$\endgroup\$ Commented Sep 14, 2023 at 18:12
  • \$\begingroup\$ @TimWilliams not sure I follow.. return currents can be through anything. But when we assume that each IC has a power supply cap to ground, then Ground currents can easily return to their source through this cap and the (assumed) gnd plane. Nothing else needed. In a high current switch circuit with the intentional return copper 1mm below and an analog trace right above will give far more issues than vice versa. And if these transient analog levels trigger stuff that shouldn't happen, it is a reliability issue IMO. \$\endgroup\$
    – tobalt
    Commented Sep 14, 2023 at 18:31
  • \$\begingroup\$ @TimWilliams as always it depends on requirements. for some generic microcontroller project with a single power node and low frequency signalling, a power plane might help achieve small board size. For stuff with many different power rails or lots of high frequency, or mixed signal, having more ground planes and low frequency traced power distribution networks with local HF decoupling can bring down layer count. \$\endgroup\$
    – tobalt
    Commented Sep 14, 2023 at 18:34

It's pretty straightforward: You give up layer that can be used for other things. Routing power without a plane is a pain though because it tends goes everywhere.

The only reason to have two ground planes on 4 layers is if they are on the outside as a shield.

Is your circuit so noise sensitive you need the shield? Or so high frequency you absolutely need the capacitive plane coupling? Is your signal density so high and your power routing so sparse that you are getter off with a third signal layer? Probably not. In which case, ease of routing trumps.

  • 2
    \$\begingroup\$ You might also use two ground planes on the inner two layers if you need to put microstrip on both outer layers. But that's a rare requirement in itself. \$\endgroup\$
    – Hearth
    Commented Sep 14, 2023 at 15:35
  • \$\begingroup\$ @Hearth Nothing wrong with microstrip over power plane, in the average case. It's an even rarer requirement, then, that you need to do that and need signal quality good enough that it can only be routed over GND (e.g. extremely low jitter timing circuits, analog/RF signals). \$\endgroup\$ Commented Sep 14, 2023 at 17:27

Making a VCC plane is a good idea if it is relatively tightly coupled to the reference GND plane.

It is true that a VCC plane and GND plane will act as a decoupling capacitor but it will be dependant of the area and distance between the 2 planes as described here.

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Your idea of having 2 GND planes is also valid and is well explained in this webinar in the question section. What he is saying is that the energy of a signal or power net are traveling in the dielectric space between the planes and you want to avoid mixing them together (really interesting webinar and suggest listening to all of it).

For my part, I can tell you that I have designed a 4 layer PCB with 1-Signal, 2-Gnd, 3-Power, 4-Signal stackup, relatively low speed digital interfaces of 100 MHz and it passed EMC tests.

In your case, it is really a tradeoff between having an easier design to route and a better signal integrity / interference immunity.


But A thing I can't elucidate if it's a good idea to make a VCC plane at all. In some cases people say that having a GND and VCC planes separated by a dielectric acts as a decoupling capacitor

A normal 4 layer stackup only has about ~1-3pf/in^2, so you would be getting not much decoupling. The decoupling would help with high frequency signals in the 100MHz+ range, many designs are not worried about 100MHz+.

But the real thing that a good design has is a good continuous ground plane. The reason for doing this is to reduce inductance and resistance on the ground plane. The power plane need not cover the whole power plane layer, and could consist of traces and/or polgyon pours that carry different power planes. RF designs will need more consideration on power plane design to ensure that power planes don't radiate.

If your design doesn't have signals that are 50MHz+ then the ground and power design is not as critical. If you have transmission lines then you will need a continous ground plane for these signals (or you can use decoupling caps, but that is a long story to explain that).

For most 4 layer designs, I have a ground layer and power layer in the middle, the main signal layer goes directly adjacent to the ground layer usually on the top layer. Bottom layer is also signal but the slower signals go on this layer.


The other answers here are mainly concerned with capacitance between planes, so I will consider the inductance instead.

A plane pair acts as a nearly ideal connection between vias.

Without going into great detail explaining how/why (transmission lines, waves, etc.), the plane impedance at high frequencies also behaves similarly to the sheet resistance between points. Which, because current spreads out, the impedance is not simply proportional to the distance between points, but is nearly a fixed amount.

We still have to be mindful of resonances or reflections within the structure, but if everything is well-behaved (i.e., we've done our job and ensured a well-damped system), the transmission line impedance will be representative of the impedance at frequencies where it's relevant (i.e., wavelength on par with or smaller than dimensions).

  • Inductance is proportional to via length, plus a modest margin proportional to plane separation/height.
  • Larger diameter vias, or clusters of smaller ones, reduce inductance.
  • Larger the plane is, the lower frequencies to which it extends, and with lower impedance (limited of course by the above factors).

And of course, you can gain some cancellation close-in by alternating vias, assuming it doesn't cost you any trace length in the process, and the resulting swiss cheese of both planes doesn't worsen things (i.e. at some point, more vias makes things worse; that'll be a pretty high density though).

Planes as Transmission Lines

Just to set the stage, or whet the appetite, or drop some keywords for further study, I will discuss transmission lines briefly.

The transmission line impedance of a plane pair (assuming a line wave traveling along some axis) can be very low indeed: a few ohms is common.

For the parallel-plate transmission line, impedance is \$Z_0 = \sqrt{\frac{\mu}{\epsilon}}\frac{h}{w}\$, where h is the height (dielectric thickness), w the width (board width, say), and μ and ε are the magnetic and electric constants, in this case μ = μ0 and ε = ε0k where k is the dielectric constant, typically 4-4.8 for common PCB materials. (We could have a relative permeability as well, and indeed, magnetically-loaded laminates, or cables, are available as specialty items.)

For a PCB of typical size, say 10cm wide and 1mm thick, we get a transmission line impedance of 1.7 ohms. That's pretty low for an electromagnetic structure.

Now, we don't get line waves* in real PCBs, not without some work anyway. When we make a via connection to a plane, we're dropping a cylinder through a hole in one plane, to contact the other. The cylindrical section looks like a piece of coax (so, of nominal impedance, ballpark 50 ohms say), of short length (~1mm), and it couples to the plane with a circular wavefront -- it looks like a point source in the plane. That is, any disturbance we make at the via, propagates outward radially, which means the wavefront is circular and therefore its perimeter increases proportionally to time. Which means the effective width of the wave increases, and so its impedance decreases as it propagates.

*Note for waves confined between planes like this, the concept of a plane wave (in free space) reduces to a line wave.

Since impedance falls with distance, it rises with frequency, which is to say: it's inductive. The rate of increase is gradual (logarithmic), so for typical design cases, we can say it's in a ballpark proportional to via size and plane spacing, and not worry too much about the distance between vias on the plane.

So, it acts as a nearly ideal conductor. Whereas trace inductance is proportional to length, the same is not true (or much less true) of the impedance between vias spread around the plane.

This means, if you can afford a couple nH between IC pins and bypasses, you can sink the pins directly to the plane, and, not really care at all about where the bypass caps are -- they can be spread about indiscriminately, and the supply acts as a nearly ideal source. And they serve equally well for any loads on the board (assuming currents aren't coherent between loads), so you can potentially save on parts count.

If you still need local bypass, you certainly still can use them, and you can have bypass caps placed locally to share impedance with the plane -- more vias, more connections to pads, more paralleling of everything.

Note that, by the same reason, you can't get an ideal connection to the plane, anywhere at all; it's always through vias. At best you can use a ton of them, all acting in parallel. Which makes a lot of sense; the plane is massively parallel itself, and it must take a wide connection (that is, many vias in parallel) to tame it.

  • 1
    \$\begingroup\$ Todd Hubing has called this decoupling scheme "global decoupling" in his educational material. not sure if it is a generally recognized term for further search. but it is indeed a very useful technique. the caps also make sure that return currents can cross between the power and ground planes, so keeping them close to signal vias is useful. \$\endgroup\$
    – tobalt
    Commented Sep 15, 2023 at 4:35
  • \$\begingroup\$ maybe mention a drawback. you see a lot of common impedance coupling between consumers which is why this can be bad for power hungry stuff or precision/analog signals. at 1 ohm impedance, a 1 A current spike will droop 1 V, which gets into the ballpark where digital things can get upset. \$\endgroup\$
    – tobalt
    Commented Sep 15, 2023 at 4:39

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