So I want to access all my ram contents in the same time. As in I want to store my 16 ram contents in 16 reg variables and then pass them onto some functions and then insert back into the ram. I want to do this mainly due to the calculation time will be long if I take only a single ram content per cycle and then perform calculations on it. This is my normal ram module:-

module ram(clk,rst,inbus,outbus,addr,we,load_finished);
input clk,we,rst;
input [7:0]inbus;
output reg [7:0]outbus;
input [4:0]addr;
output wire load_finished;
always @(posedge clk)begin
                for(integer i=0;i<16;i=i+1) mem[i]<=0;
          else begin            
                if (we)mem[addr] <=inbus;
               else outbus<=mem[addr];      
assign load_finished=(we)? 0:1;

Any help will be greatly appreciated


1 Answer 1


You want a register file for this, not a ram. Just declare an array of registers in your RTL, not as a separate module.

reg [7:0] regfile[0:15];
  • \$\begingroup\$ can the arrays be an array of wire instead and be then directly connected to other modules? as .var1(regfile[0]), .var2(regfile[1],) , .var3(regfile[2]) .....etc \$\endgroup\$
    – Rezef
    Sep 16 at 5:59
  • \$\begingroup\$ Yes. If you can use SystemVerilog, a single port can be an array. \$\endgroup\$
    – dave_59
    Sep 16 at 6:32

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