I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them.
My understanding so far:
To calculate the set_output_delay I simply need to look at the setup and hold times.
The setup time is becomung the max setup_output_delay and the negative hold time is becoming the min set_output_delay.
What I didn't fully understant until now is the set_input_delay constraint.
My understanding here is that I need the Output LOW Impedance time and Output HIGH Impedance time on the SDRAM side and some respective values on the FPGA side.
While I could find the values in the sdram datasheet I can't find anything looking like something I need in the FPGA datasheet.
I'm using a DE2-115 board with a IS42S86400B SDRAM and an EP4CE115f29c7 FPGA.
My (obvious) questions:
Is my understanding of the set_output_delay correct?
What am I missing when calculating the set_input_delay?
When I try the attached sdc file, the timing analyzer fails using the Slow 1200mV 85C and the Slow 1200 0C model while successing using the Fast 1200mv 0C model with a tiny positive slack. I tried my own SDRAM controller and the IP SDRAM Controller integrated in Quartus using a phase shift of -3ns for the sdram clock as it is used in the example projects of that board.
My sdc file so far:
#**************************************************************
# Create Clock
#**************************************************************
create_clock -period 20.000ns [get_ports clock_50]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -clock u0|altpll_1|sd1|pll7|clk[1] -max 5.5 [get_ports dram_dq*]
set_input_delay -clock u0|altpll_1|sd1|pll7|clk[1] -min 0.0 [get_ports dram_dq*]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -clock u0|altpll_1|sd1|pll7|clk[1] -max 1.5 [get_ports dram*]
set_output_delay -clock u0|altpll_1|sd1|pll7|clk[1] -min -0.8 [get_ports dram*]
