# I am designing a 4-bit Carry Look Ahead Adder, but it doesn't work correctly

I am new to Verilog. I am asked to write a gate-level design of a CLA adder. The equation is:

generate'' signal gi = ai . bi

propagate'' signal pi = ai ⊗ bi

carry'' signal Ci = (C0 . p0 . p1......pi)+(g0 . p1 . p2....pi) +(g1 . p2 . p3....pi) +(gi-1 pi) + gi

sum'' signal Si = Ci-1⊗ ai ⊗ bi=Ci-1 ⊗ pi


Just like the title, my adder doesn't work. My inputs: a = 4 b = 7, cin=0, but my output: s = 5. Here's my CLA_adder code:

module CLA_adder(a, b, ci, s);

input[3:0] a, b;
input ci;
output[3:0] s;

wire [3:0] p, g, co;
wire [3:1] c;

FA GG0(a[0],b[0],ci,g[0],co[0]);
FA GG1(a[1],b[1],co[0],g[1],co[1]);
FA GG2(a[2],b[2],co[1],g[2],co[2]);
FA GG3(a[3],b[3],co[2],g[3],co[3]);

xor PG0(p[0],a[0],b[0]);
xor PG1(p[1],a[1],b[1]);
xor PG2(p[2],a[2],b[2]);
xor PG3(p[3],a[3],b[3]);

assign #10 c[1] = (ci & p[0]) | g[0];
assign #10 c[2] = (ci & p[0] & p[1]) | (g[0] & p[1]) | (g[0] & p[1]) | g[1];
assign #10 c[3] = (ci & p[0] & p[1] & p[2]) | (g[0] & p[1] & p[2]) | (g[1] & p[2]) | (g[1] & p[2]) | g[2];

xor #10 SG0(s[0], ci, p[0]);
xor #10 SG1(s[1], c[1], p[1]);
xor #10 SG2(s[2], c[2], p[2]);
xor #10 SG3(s[3], c[3], p[3]);
endmodule

module FA(a_in, b_in, c_in, s_out, c_out);

input a_in, b_in, c_in;
output c_out, s_out;

wire w1, w2, w3;

xor(w1, a_in, b_in);
xor(s_out, w1, c_in);
and(w2, w1, c_in);
and(w3, a_in, b_in);
or(c_out, w2, w3);

endmodule


My simplest testbench:

module tbCLA_adder();

reg [3:0] a, b;
reg ci;
wire [3:0] s;

CLA_adder DUT(.a(a), .b(b), .ci(ci), .s(s));

initial begin
a = 4 ; b = 7; ci = 0;
#30;
end

endmodule


You did not implement the generate equation properly. You used full adders, but the equation specifies AND gates. This produces the correct output (s=11):

module CLA_adder(a, b, ci, s);
input[3:0] a, b;
input ci;
output[3:0] s;

wire [3:0] p, g;
wire [3:1] c;

and GG0(g[0],a[0],b[0]);
and GG1(g[1],a[1],b[1]);
and GG2(g[2],a[2],b[2]);
and GG3(g[3],a[3],b[3]);

xor PG0(p[0],a[0],b[0]);
xor PG1(p[1],a[1],b[1]);
xor PG2(p[2],a[2],b[2]);
xor PG3(p[3],a[3],b[3]);

assign #10 c[1] = (ci & p[0]) | g[0];
assign #10 c[2] = (ci & p[0] & p[1]) | (g[0] & p[1]) | (g[0] & p[1]) | g[1];
assign #10 c[3] = (ci & p[0] & p[1] & p[2]) | (g[0] & p[1] & p[2]) | (g[1] & p[2]) | (g[1] & p[2]) | g[2];

xor #10 SG0(s[0], ci, p[0]);
xor #10 SG1(s[1], c[1], p[1]);
xor #10 SG2(s[2], c[2], p[2]);
xor #10 SG3(s[3], c[3], p[3]);
endmodule


There is no need for the full adder.

Note that you used a mixture of gate-level and behavioral (assign) modeling.

• (I don't see use in (g[0] & p[1]) | (g[0] & p[1]), (g[1] & p[2]) | (g[1] & p[2]).) I might argue an additional terminal co(=c3). Sep 17, 2023 at 3:19