# I am designing a Carry-Save Adder, but my output waveform is all StX

My CSA has ten 5-bit binary inputs, and one 9-bit output with a carry-out. I am trying to use full adder to realize the function. I have two 3 stages CSA to get two output sets (sum and count) and I use full adder to get my result. Here is my code:

module CSA(
input [4:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,
output [8:0] s,
output cout
);
wire[4:0] s1, s6;
wire [5:0] s2, s7;
wire [6:0] s3, s8;
wire [7:0] s4, s9;
wire [8:0] s5, s51, s10,s101;

wire [5:1] c1,c6;
wire [6:1] c2,c7;
wire [7:1] c3,c8;
wire [8:1] c4,c9;
wire [9:1] c5,c10;

genvar i;
generate
for (i = 0; i<5; i = i + 1) begin
FA fa_inst10(a0[i],a1[i],a2[i],s1[i],c1[i+1]);
FA fa_inst11(a6[i],a7[i],a8[i],s6[i],c6[i+1]);
end
endgenerate

FA fa_inst20(1'b0, s1[0], a4[0],s2[0],c2[1]);
FA fa_inst21(1'b0, s6[0], a9[0],s7[0],c7[1]);
generate
for (i = 1; i < 6; i = i + 1) begin
FA fa_inst201(c1[i],s1[i],a4[i],s2[i],c2[i+1]);
FA fa_inst211(c6[i],s6[i],a9[i],s7[i],c7[i+1]);
end
endgenerate

FA fa_inst30(1'b0, s2[0], a5[0], s3[0], c3[1]);
FA fa_inst31(1'b0, s7[0],a9[0],s8[0],c8[1]);
generate
for (i = 1; i <6; i = i + 1) begin
FA fa_inst301(c2[i],s2[i],a5[i],s4[1],c4[i+1]);
FA fa_inst31(c7[i], s7[i],a9[i],s8[i],c8[i+1]);
end
endgenerate

FA fa1(s4[0], 1'b0, 1'b0, s5[0], c5[1]);
FA fa2(s9[0],1'b0,1'b0,s10[0],c10[1]);
generate
for (i = 1; i < 8; i = i + 1) begin
FA fa10(s4[i],c4[i],c5[i],s5[i],c5[i + 1]);
FA fa20(s9[i],c9[i],c10[i],s10[i],c10[i+1]);
end
endgenerate

assign s51[8] = c5[8];
assign s51[7:0] = s5[7:0];

assign s101[8] = c10[8];
assign s101[7:0] = s10[7:0];

wire [9:1] c_out;
FA sum0(s51[0],s101[0],1'b0,s[0],c_out[0+1]);
FA sum1(s51[1],s101[1],c_out[1],s[1],c_out[1+1]);
FA sum2(s51[2],s101[2],c_out[2],s[2],c_out[2+1]);
FA sum3(s51[3],s101[3],c_out[3],s[3],c_out[3+1]);
FA sum4(s51[4],s101[4],c_out[4],s[4],c_out[4+1]);
FA sum5(s51[5],s101[5],c_out[5],s[5],c_out[5+1]);
FA sum6(s51[6],s101[6],c_out[6],s[6],c_out[6+1]);
FA sum7(s51[7],s101[7],c_out[7],s[7],c_out[7+1]);
FA sum8(s51[8],s101[8],c_out[8],s[8],cout);
endmodule

module FA(a_in, b_in, c_in, s_out, c_out);

input a_in, b_in, c_in;
output c_out, s_out;

wire w1, w2, w3;

xor(w1, a_in, b_in);
xor(s_out, w1, c_in);
and(w2, w1, c_in);
and(w3, a_in, b_in);
or(c_out, w2, w3);

endmodule


Is there anything I wrote wrong here?

Edited: Testbench:

module tbCSA;

reg [7:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9;
wire [8:0] s;
wire cout;
CSA uut (a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,s,cout);

initial begin

#50
a0 = 11;
a1 = 2;
a2 = 13;
a3 = 4;
a4 = 5;
a5 = 6;
a6 = 7;
a7 = 8;
a8 = 9;
a9 = 10;

#50

a0 = 3;
a1 = 14;
a2 = 5;
a3 = 6;
a4 = 7;
a5 = 8;
a6 = 19;
a7 = 10;
end
endmodule

• Sorry for forgetting to vote on your valuable answer. It does help me modify my code. Thanks! Commented Sep 17, 2023 at 23:38
• Maybe I'm wrong here, but isn't this a programming question? You posted in EE. Commented Sep 17, 2023 at 23:45
• I think EE includes Verilog and hardware, maybe? Commented Sep 17, 2023 at 23:46
• Ok I stand corrected. But give it some time, your question only got 13 views so far. Commented Sep 17, 2023 at 23:48
• Post your testbench code so we can run a sim. Post waves that show what signal is X and at what time. Also, add description of what your code should do. Should it add all 10 inputs? Commented Sep 17, 2023 at 23:49

The simulators I used generate several compiler warnings and errors. If your simulator does not show any warnings or error, use the free simulators on EDAPlayground.

For example, you have bit-width mismatches in your testbench. You connected 8-bit signals to 5-bit ports.

Change:

reg [7:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9;


to:

reg [4:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9;


Then, you have out-of-bounds errors in your generate blocks. For example:

    FA fa_inst201(c1[i],s1[i],a4[i],s2[i],c2[i+1]);
|
xmelab: *SE,BNDBERR (./tb.sv,30|25): Bit-select index [5] is out of declared bounds [4:0] for 's1'
of the instance (tbCSA.uut.genblk2[5])(./tb.sv,6|15).


You need to fix all errors and warnings.

• I just did it right and posted my correct code below. Thanks for the help again Mr. toolic. Commented Sep 18, 2023 at 0:38

Just did it! Both my CSA and test modules have many problems. Here's the right code:

module CSA(
input [7:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,
input cin,
output [11:0] s,
output cout
);

wire [8:0] s1,c1,s2,c2;
wire [9:0] s3,c3,s4,c4;
wire [10:0] s5,c5,s6,c6;
wire [11:0] sum1, sum2;
wire cout1,cout2;

endmodule

input[9:0] A,B;
input cin;
output[9:0] sum;
output cout;

wire[9:0] carry;

genvar i;
generate for(i = 0; i<10;i=i+1) begin
if(i==0)
FA fa(A[i],B[i],cin,sum[i],carry[i]);
else
FA fa(A[i],B[i],carry[i-1],sum[i],carry[i]);
end
endgenerate
assign cout = carry[9];

endmodule

input[7:0] x,y,z;
output[10:0] sum,cout;
genvar i;
generate for (i=0;i<10;i=i+1) begin
FA fa(x[i],y[i],z[i],sum[i],cout[i+1]);
end
endgenerate
assign cout[0] = 1'b0;

endmodule

module FA(a_in, b_in, c_in, s_out, c_out);

input a_in, b_in, c_in;
output c_out, s_out;

wire w1, w2, w3;

xor(w1, a_in, b_in);
xor(s_out, w1, c_in);
and(w2, w1, c_in);
and(w3, a_in, b_in);
or(c_out, w2, w3);

endmodule


TB:

module tbCSA;

reg [7:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9;
reg cin;
wire [11:0] s;
CSA uut (a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,cin,s);

initial begin
cin = 0;

#50
a0 = 8'b00001011;
a1 = 8'b00000010;
a2 = 8'b00001101;
a3 = 8'b00000100;
a4 = 8'b00000101;
a5 = 8'b00000110;
a6 = 8'b00000111;
a7 = 8'b00001000;
a8 = 8'b00001001;
a9 = 8'b00001010;

#50

a0 = 8'b00000011;
a1 = 8'b00001110;
a2 = 8'b00000101;
a3 = 8'b00000110;
a4 = 8'b00000111;
a5 = 8'b00001000;
a6 = 8'b00010011;
a7 = 8'b00001010;
a8 = 8'b00000000;
a9 = 8'b00000000;
end

endmodule