Ground Relief Gap Design Rule -- Altium

Question

Does anyone know of a way to implement a design rule in altium to check for instances where signals cross over a via relief ground plane gap? Example shown below.

Thanks!

Answer 1

There are only specific built-in between-layer checks; you cannot create your own (e.g. by trying to query objects on a different layer).

You might be able to create your own via scripting, but that's a whole thing detecting relevant objects, locating relevant geometry, and comparing them in such a way to produce the desired detection. And doing it fast enough that it doesn't take forever to run the check (i.e., not accidentally quadratic runtime).

If this specific case is the one that's bothersome (GND plane relief on vias near traces), I would make two recommendations:

1. Disable thermal relief on vias. It's not needed, and introduces problems (like this!).
2. Consider changing to polygon instead of plane. Altium's plane features are heavily dated, and polygons are recommended. (They may've improved them in recent versions, I'm not sure.)

Also if I may read into the net names, if "FMC" as in STM32 Flash Memory Controller, the edge rate of these signals (ballpark 2 ns) is far, far lower than this mm-scale feature will have an effect upon. Your concern is only an extremely high frequency (or high precision) one: if you're working with say 6Gbps+ signals, or microwaves, or somewhat lower frequencies at extremely tight precision (fractional dB flatness, or precision of impedance, say), then it may be a concern. Also if you have signals opposite the plane, the openings allow some field to couple through (which, if it's a plane pair, obviously that's N/A).