I'm currently trying to simulate a VHDL module with a SV testbench.

The VHDL module contains several packages that are compiled into various libraries so in order to avoid compile errors within the VHDL module I need to compile the packages into the correct library

vcom -2008 -mixedsvvh -work grlib "../../../../grlib-com/lib/grlib/amba/amba.vhd"

My issue arises when trying to import (import amba::*;) the amba package into my SV testbench. I keep getting the following error: (vlog-13006) Could not find the package (amba). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command

The error disappears when I also compile the package into the work library, however, it gets replaced by the following error the type of vhdl port 'ahbsi' is invalid for verilog connection (the ahbsi record type is within the amba VHDL package)

(should also note that I call vsim as follows: vsim -voptargs="+acc" -64 -L grlib work.testbench )

Is there anyway to import the amba package directly from the library I compiled to? (grlib in this case) or does it have to also be compiled into the work library?

Edit: I compile the sv file that the import is called from as follows: vlog -sv -work work "../dpram_test/dpram_tb.sv"


1 Answer 1


You need to add the -L grlib to vlog as well as using it with vsim.

Can't say what might be wrong with your ahbsi record type without seeing it. You should refer to Table 8-27. Supported Types Inside VHDL Records in the Questa User Manual.


  • The default work library is work, so -work work is redundant
  • You should not be using vlog -sv switch unless absolutely necessary. The compiler automatically recognizes *.sv files as SystemVerilog. The compiler will throw an error if you have legacy Verilog files that use SystemVerilog keywords. This is because SystemVerilog is an extension of Verilog and contains additional features that are not present in Verilog . If you use SystemVerilog keywords in a Verilog file, the compiler will not recognize them and throw an error

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