Confused about STM32 FMC pins for SDRAM

Question

Context: I am currently working on a design that is centered around the STM32H723ZGEI6. I chose to opt for 32MB of external RAM via the IS42S16160J SDRAM IC. However, I am having some trouble figuring out how to connect some of the pins.

Problem: I don't understand what the NBL0, NBL1 or SDNE pins do, or to what they should connect? I've looked through a few app notes, but I still can't seem to find anything that properly clarifies it for me.

I have attached both sections of the schematic below. Any help would be greatly appreciated; this is my first attempt at designing anything with external RAM.

Note: Although not related, schematic criticisms are also welcome.

Schematic page for STM32H723:

Schematic page for IS42S16160J SDRAM:

Answer 1

The NBL[1:0] pins are byte enables for the data bus - NBL0 selecting whether to enable the lower byte, and NBL1 the upper byte. For devices with 32bit FMC, you would have NBL[3:0] selecting the corresponding bytes.

Your memory provides the ability to mask the upper and lower bytes through the DQML and DQMH pins. So in this case you would want to connect NBL1 to DQMH and NBL0 to DQML.

The NBL signals are prefixed with an N which according to the reference manual (link below, section "22.7.1 External memory interface signals") indicated active low signals (low = enabled). Your memory indicates that it sets the corresponding data pins to High-Z when the DQMx pins are high. They seem therefore to be matching polarity (as one might expect).

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The SDNE pin is the SDRAM "Not Enable" pin. This is set high to disable the RAM. This is equivalent functionality to the C̅S̅ pin for your RAM. So you would connect SDNE to C̅S̅.

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You can find further details about the pins for the external memory controller in the Reference Manual for the part. Section 22 covers the external memory interface.