MPQ4470-AEC1 Layout guideline clarification

Question

I am using MPQ4470-AEC1 in my design. In the datasheet page no 18 contains the layout guidelines.

I have some questions about guideline no:2 and no:3 .Those guidelines are given below.

1. Place input capacitors on both VIN sides (PIN8 and PIN19) and as close to the IN and GND pins as possible.
2. Place the decoupling capacitor as close to the VCC and GND pins as possible

Regarding placement, they said only 'close'.

My question is how to calculate the maximum and minimum distance away from the IC so that I can place the parts (capacitor).

Answer 1

No, the datasheet does not say only "close". What is says is "as close as possible". Therefore, if it is possible to move a capacitor closer, then it is too far away.

The goal of these guidelines is to minimize the inductance of the traces between the chip and the capacitors. A switching power supply needs to generate quick current changes, but inductance would slow them down.

This is an analog property. Longer traces result in progressively worse effects. And the effects on the working of the supply or on EMC depend strongly on your layout and the environment, so it is impossible to predict or compute where the limit would be. So saying "as close as possible" is the only practical way to reduce the risk of a bad layout.