Page 166 of datasheet of atmega328 shows the use of a register called
When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode.
No sign of it in the
io.h file associated with the atmega328, nor in the register summary section. Where I can find infos about it ?