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Page 166 of datasheet of atmega328 shows the use of a register called DDR_XCK.

When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode. 

No sign of it in the io.h file associated with the atmega328, nor in the register summary section. Where I can find infos about it ?

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  • \$\begingroup\$ PD4 in atmega328 is XCK pin. So the Data Direction Register for the XCKn (PD4) pin is DDRD register. \$\endgroup\$
    – G36
    Commented Sep 22, 2023 at 6:09

1 Answer 1

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Section 13.2, There you have the data direction registers for every port, just choose the register and bit that matches your clock pin (XCKn)

it's definitely not written in the most clear way

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