STP08DP05 Truth table clarification

Question

Can someone explain exactly when the STP08DP05 clocks data into the shift register and when data appears on the output?

In the datasheet (p. 10) the truth table is more confusing than helpful for me.

I was under the impression that OE and LE were asynchronous. I.E that I could use LE after I had clocked in data to make the internal state appear at the output and that I could PMW the OE to dim the outputs. However, the datasheet only has entries for state changes on clock edges.

How is the truth table meant to be interpreted?

Answer 1

By experimentation I found that OE and LE are asynchronous as expected. However it seems data is shifted into the shift register on the falling edge. i.e data should be stable on the falling edge. I don't know why the data sheet says otherwise, but if I change the polarity the outputs will be unstable.

As expected LE should be asserted when the data is stable, so after the last bit has been fully shifted.

As long as the LE line is asserted the DATA will travel from the shift register to the output buffer. To avoid the outputs from flickering it should not be asserted while the data is changing. i.e. don't clock and LE at the same time...

OE is asynchronous and can be asserted at any time to actually enable the outputs, or PWMed to dim them.

Care should be taken to avoid activating the debug mode by sending the special sequence which is the only case in which OE and LE can be considered synchronous to the clock.