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I have the following common emitter amplifier circuit.

enter image description here

enter image description here

I am also told that, when taking the specs above,to consider a 20% safety margin to accommodate for possible parameter variability.

Then there are a few questions:

a) Attending to PD, one can provide an estimate for the upper limit of the total current in the circuit. The current through RB1 can be arbitrated to about 1/10 IC. Based on this approach, establish a value for the quiescent current IC.

To find Ic i did the scheme:

enter image description here

And figured that the power dissipation of the circuit would be the power dissipation of both voltage sources.

Since (P = V x I) and Irb1 = Irb2; Ic = Ie, i would have this formula for the power dissipation:

  • 6 x (11/10)Ic + (11/10)Ic x (-6) = 18m.

I am supposed to obtain Ic through that equation, but it is obviously incorrect.

((11/10)Ic = Ic + (1/10)Ic, representing the current created by the tension sources. )

I am hoping someone can help me understand how i am supposed to equate this problem and figure Ic.

Another question related to this problem i am having trouble with:

b) From the signal swing limits stated in the specs, define VC and verify if the total spec is reachable.

I have previously discovered

  • RE = 917 ohm
  • VE = -5 V
  • VRE = 1V (Tension across RE)

(Because i was told that Ic = 1.09mA. I still don't know how to get there though)

In this question i know the swing limits are 6V.

I think the way to do this is to transform the circuit in its equivalent to DC and just figure VC through circuit analysis. I am having trouble with that because i dont have any values for RC, Rb1 or Rb2.

enter image description here

I would apreciate any help :)

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  • \$\begingroup\$ But the power dissipation is not the power consumption. The power dissipation Pd = Vce*Ic. \$\endgroup\$
    – G36
    Commented Sep 23, 2023 at 16:29
  • \$\begingroup\$ @G36: The static dissipation and the static consumption the same and incudes the dissipation in the resistors. \$\endgroup\$
    – RussellH
    Commented Sep 23, 2023 at 18:03
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    \$\begingroup\$ Strange, but okay. In that case, the total supply current cannot be larger than 18mW/12V = 1.5mA. As for the voltage swing 3V/47k = 64uA So we can pick Ic --->20*64uA = 1.2mA or so. RE = 1V/1.2mA = 820R or 1K (E12). If we pick 1k we bave V_RE = 1.2V . And RC = ((12V -1.2V)/2)/1.2mA = 5.4V/1.2mA = 4.7k (E12). \$\endgroup\$
    – G36
    Commented Sep 23, 2023 at 18:23
  • \$\begingroup\$ @G36 Can you explain where does the 20 in your multiplication to find Ic comes from? (Ic = 20*64uA). Also to find RC, shouldn't it be : [(12V - 1,2V - 0,7V)/2]/1.2mA? (The 0.7V from Vbe). \$\endgroup\$
    – Aleat
    Commented Sep 23, 2023 at 18:57
  • \$\begingroup\$ No, the Vbe is not a part of the output loop. The output loop is Vcc+Vee = VRc + Vce + Ve. As for the Ic current. The quiescent collector current should be much larger than the ac load current. At least ten times to get "low distortion". I used a factor of 20 instead of 10. \$\endgroup\$
    – G36
    Commented Sep 23, 2023 at 19:16

3 Answers 3

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I find the problem given interesting in a few ways:

  1. For questions I've seen here, it's unusual to see a specific mention of a "20%" variation in parameters. I take to mean BJT parameters as E12 resistors don't vary that much and, while capacitors do, their values in a circuit like this only need to be large enough to serve the need.
  2. Both the source and load impedances are included. I don't see that happen as often as I'd like.
  3. It's unusual for me not to see an explicit gain specified. But there are other factors that can dictate this. (Such as, for example, the voltage across \$R_{_\text{E}}\$.) So no worries, in particular. You mention "I have previously discovered..." and there suggest \$\mid\: V_{R_{_\text{E}}}\mid\:=1\:\text{V}\$, so I'll discuss that, too.

Let's start with #1; the 20% variation in parameters of the BJT. There are three parameters that matter here, \$\beta\$, \$I_{_\text{SAT}}\$, and \$V_A\$. All of these alter the DC quiescent operating point. But only \$I_{_\text{SAT}}\$ matters enough to cause anything near 20% variation.

Some thoughts:

  • The collector current is in the vicinity of \$1\:\text{mA}\$. While the high-\$\beta\$ BC547C device does have an attending crappy \$V_A\$ (tends to go hand-in-hand) of around \$50\:\text{V}\$, this means an added \$50\:\text{k}\Omega\$ across the collector-emitter and given that your collector resistor is likely to be more than 50X smaller, it's just not going to impact things by 20%. (It will slightly reduce the resulting gain.)
  • \$\beta\$ is really high, as stated at \$\beta=400\$. (This is kind of low for the C part with the Fairchild datasheet saying that the minimum is 420.) And you are permitted a fairly stiff divider pair because of the allowance of \$18\:\text{mW}\$. So a 20% change in base current, which will be less than 2% of the divider pair current, won't upset the biasing by more than 2%. Likely less. That said, \$\beta\$ variation is almost always greater than 20%. So a strong argument can be made that the lesson's limiting of 20% is unrealistic here. So perhaps \$\beta\$ should be kept in view. But the problem statement says "no." So either I go with that or disagree with it. A choice must be made. My choice is to look at it and let you decide.
  • Now we get to \$I_{_\text{SAT}}\$. Again, here, a 20% variation will only account for \$V_T\cdot\ln\left(\frac{1+20\%}{1-20\%}\right)\$ or about \$10\:\text{mV}\$ on \$V_{_\text{BE}}\$. That's around 1.5% variation. So that's not going to qualify.
  • But again, \$I_{_\text{SAT}}\$ variation is a lot more than 20%, part to part, too. 100% or more. So on this last point I have to think they meant to directly address \$V_{_\text{BE}}\$ with only an indirect implication for \$I_{_\text{SAT}}\$. Taking that as their purpose then this can significantly impact the biasing of \$R_{_\text{E}}\$ and therefore \$I_{_\text{Q}}\$ and therefore the circuit itself. However, we run into another problem because of the implications of variations on \$I_{_\text{SAT}}\$, as this makes a claim that such variation is over four orders of magnitude change. And that also doesn't happen.

So what does all that mean when someone says to account for a 20% variation in parameters? Especially when taking a cargo cult value of \$V_{_\text{BE}}= 700\:\text{mV}\$ (which a quick look at a datasheet confirms) and then from there claiming \$560\:\text{mV} \le V_{_\text{BE}}\le 840\:\text{mV}\$, when a more likely range might be \$680\:\text{mV} \le V_{_\text{BE}}\le 720\:\text{mV}\$?

Well, perhaps the answer is about temperature variation of \$V_{_\text{BE}}\$, which can vary by a couple of millivolts per Kelvin (with varying rates of change depending upon the absolute temperature.) The writing above is trye when the temperature is considered unvarying. But adding temperature variation does matter. Here, assuming \$\pm 30\:\text{C}^\circ\$, then perhaps \$560\:\text{mV} \le V_{_\text{BE}}\le 840\:\text{mV}\$ might actually arise. So I'm thinking that the author is talking only about \$V_{_\text{BE}}\$ and including not only part variation but also all reasonable operating temperature variations, too.

Note that it takes all of these machinations just to figure out the meaning of #1 above.

How do you keep a circuit's operating point stable over such wide temperature variations? In this case, by increasing the quiescent voltage drop across \$R_{_\text{E}}\$. If it's large enough, then even \$\pm 140\:\text{mV}\$ variation won't matter much. The larger the voltage magnitude you can throw onto \$R_{_\text{E}}\$, the better (for a stable quiescent point, I mean.)

Since no gain is specified, you could technically make the circuit very stable! But I'll be reasonable.

There are many rules of thumb. One of mine is that only under the most dire circumstances may the BJT become even slightly saturated. This will mean that \$V_{_\text{CE}}\$ must never have a smaller magnitude than \$1\:\text{V}\$. But I prefer \$2\:\text{V}\$. This has to do with safety margins to avoid saturation, in some part, but also to avoid gain variation (distortion) over signal input variation. Again, the more I can throw at it, the better. But here, I'd start with \$V_{ _{\! \text{CE}_\text{MIN} } }=2\:\text{V}\$.

This means there's only \$4\:\text{V}\$ left over to split between collector and emitter resistors at the worst case temperature (at the hot end of things where \$I_{_\text{Q}}\$ is at its maximum value.) Given the \$280\:\text{mV}\$ I also have to reserve out for variation of \$V_{_\text{BE}}\$, I'd select a quiescent \$\mid\: V_{R_{_\text{E}}}\mid\:=2\:\text{V}\$ and leave the rest for the minimum drop across \$R_{_\text{C}}\$.

Power dissipation says that the total quiescent stage current cannot exceed \$1.5\:\text{mA}\$. Again, it's important to take temperature into account when reading specs like this. Given that it is a spec, it should be taken as a worst case spec. And this will be at the hottest temperature, which is where we will design at, leaving the room temperature quiescent dissipation to fall out to a lower value.

The following is based on the highest temperature in the range. So when I mention quiescent I mean `quiescent at the highest temperature':

Start at the negative rail and add reservations and an allowance for half the peak-to-peak output that must be achieved. So: \$V_{_{\text{C}_\text{Q}}}=-6\:\text{V}+2\:\text{V}+2\:\text{V}+3\:\text{V}=1\:\text{V}\$.

Given the usual rule (cargo cult-ish) that the biasing pair carry about 10% of the collector current, this means \$I_{_{\text{DIV}_\text{Q}}}=150\:\mu\text{A}\$ (or more.) But keeping \$I_{_{\text{C}_\text{Q}}}=1.3\:\text{mA}\$ will keep us under the dissipation limit and make the biasing pair just a little stiffer. Which is good.

Base current will also vary over temperature because both \$I_{_{\text{C}_\text{Q}}}\$ and \$beta\$ vary. Given that the recommended value you have is a little lower than the minimum I see on the Fairchild sheet, I'm going to just accept the value for the highest temperature in the range. So this means a base current of \$I_{_{\text{B}_\text{Q}}}=3.25\:\mu\text{A}\$.

From there we can work out the resistors:

  • \$R_{_\text{E}}=\frac{V_{_{\text{E}_\text{Q}}}-V_{_\text{EE}}}{I_{_{\text{C}_\text{Q}}}\cdot\frac{\beta+1}{\beta}}= \frac{2\:\text{V}}{1.3\:\text{mA}\cdot\frac{401}{400}}\approx 1534.6\:\Omega\$. If we pick \$1.5\:\text{k}\Omega\$ then this might put us past the dissipation limit, except that I selected a slightly lower \$I_{_{\text{C}_\text{Q}}}\$. So should be okay.
  • \$R_{_\text{C}}=\frac{V_{_\text{CC}}-V_{_{\text{C}_\text{Q}}}}{I_{_{\text{C}_\text{Q}}}}= \frac{5\:\text{V}}{1.3\:\text{mA}}\approx 3846\:\Omega\$. If we pick \$3.9\:\text{k}\Omega\$ then this might push against the output signal range margin, except again that I selected a slightly lower \$I_{_{\text{C}_\text{Q}}}\$. So maybe be okay.
  • \$R_{_{\text{B}_1}}=\frac{V_{_\text{CC}}-V_{_{\text{E}_\text{Q}}}-V_{_{\text{BE}_\text{Q}}}}{I_{_{\text{DIV}_\text{Q}}}+I_{_{\text{B}_\text{Q}}}}= \frac{9.42\:\text{V}}{150\:\mu\text{A}+3.25\:\mu\text{A}}\approx 61468\:\Omega\$. (Hold on that number, for now.)
  • \$R_{_{\text{B}_2}}=\frac{V_{_{\text{E}_\text{Q}}}+V_{_{\text{BE}_\text{Q}}}-V_{_\text{EE}}}{I_{_{\text{DIV}_\text{Q}}}}= \frac{2.58\:\text{V}}{150\:\mu\text{A}}\approx 17200\:\Omega\$. (Hold on that number, for now, again.)

There aren't any E12 values for the base biasing pair and no simple multiplier can fix it. It is safer to cause the quiescent current to drop, than rise, given the dissipation limit. So I'll set \$R_{_{\text{B}_2}}=18\:\text{k}\Omega\$ and \$R_{_{\text{B}_1}}=68\:\text{k}\Omega\$. This will cause the biasing point to be slightly lower at the emitter and that will lower the quiescent collector current, slightly.

So the final circuit has \$R_{_\text{E}}=1.5\:\text{k}\Omega\$, \$R_{_\text{C}}=3.9\:\text{k}\Omega\$, \$R_{_{\text{B}_1}}=68\:\text{k}\Omega\$, and \$R_{_{\text{B}_2}}=18\:\text{k}\Omega\$.

From KVL: \$I_{_{\text{C}_\text{Q}}}=\frac{\frac{V_{_\text{CC}}-V_{_\text{EE}}}{1+\frac{R_{_{\text{B}_1}}}{R_{_{\text{B}_2}}} }-V_{_{\text{BE}_\text{Q}}}}{R_{_{\text{B}_1}}\mid\mid R_{_{\text{B}_2}}+R_{_\text{E}}\cdot\frac{\beta+1}{\beta}}\$. (Use Thevenin and KVL from base towards emitter to work this out.) So \$I_{_{\text{C}_\text{Q}}}\approx 1.05\:\text{mA}\$ at hot temperatures and \$I_{_{\text{C}_\text{Q}}}\approx 990\:\mu\text{A}\$ at low temperatures.

Gain should be low. There should be \$-0.062\:\text{dB}\$ attenuation on the input side (not much) and \$-0.692\:\text{dB}\$ attenuation on the output side. In between, the gain should be \$+6.59\:\text{dB}\$ due to the BJT CE stage (discounting the Early Effect, \$V_A\$, mentioned before.) All in all, about \$+5.84\:\text{dB}\$ or 1.96 (about 2X.) So to get the full output, the input source should present about \$V_\text{PK}=1.5\:\text{V}\$.

Let's check all this out with LTspice:

enter image description here

Looks about right.

And with signal added:

enter image description here

Which also looks about right.

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  • \$\begingroup\$ So to determine the quiecent point you basicly just chose an Ic value below 1.5mA and a VCE above 1V? Also, to calculate VCq, why did you add the 3V? I supose those 3V are from the output swing, but why add them on VCq? \$\endgroup\$
    – Aleat
    Commented Sep 24, 2023 at 12:28
  • \$\begingroup\$ @Aleat Yes, the 3 V was added to place the center of the 6 V swing. Nothing more complicated than that. The reason for Vce above 1 V is explained -- to stay away from saturation, which causes distortion. The reasoning should be fairly simple to follow. You have a 6 V swing to handle, a minimum Ve, and a minimum Vce. You also have a minimum for the drop across RC, as well. (If it drops to zero, Ic must be zero and that would be very bad.) You want as much as you can get for Ve, for temperature reasons (DC biasing) and also for gain variation with signal reasons (distortion.) More the better. \$\endgroup\$ Commented Sep 24, 2023 at 15:03
  • \$\begingroup\$ @Aleat You didn't specify a gain. So that meant I could just talk about general goals for a low distortion output. If you need more gain, then you must sacrifice minimum Ve (and maybe some minimum Vce) and move towards more distortion if you must also keep your output swing magnitude. You could get back lower distortion with higher gain, but only if you give up some on the output swing. You can also increase Icq to lower distortion, too. But you've been given a spec there. So you can't go there. In short, everything's a trade-off. \$\endgroup\$ Commented Sep 24, 2023 at 15:07
  • \$\begingroup\$ I just haven't understood the output swing wet. Why do i add 3V in DC if what i want are 3V of amplitude on the AC signal. Adding those 3V isn't only gonna move the mid point of the swing 3V up, keeping the amplitude? \$\endgroup\$
    – Aleat
    Commented Sep 25, 2023 at 8:42
  • \$\begingroup\$ @Aleat Get out a piece of paper and draw a picture. Like this. It's really not very hard to see and understand. This isn't rocket science. \$\endgroup\$ Commented Sep 25, 2023 at 11:00
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However 'correct' Antonio's answer is, it has little didactic merit.

Power dissipation

You will notice there are no DC paths to ground. This means we can just take the power supply as 12 V.

Dissipation less than 18 mW? I assume that means for the entire amplifier, not just the transistor. 18 mW from 12 V is 1.5 mA total maximum, of which we are told to send 10% down the base bias chain (a good rule of thumb).

This means about 1.3 mA in the collector, and 130 uA in the base bias chain.

Output Swing

We want at least +/- 3 V swing at the collector, better to go for +/- 4.5 V as we have the headroom. Therefore we want to set 4.5 V across Rc with 1.3 mA flowing through it. Rc = 4.5/1.3m = 3.46k. The nearest E12 to that is 3.3k, which will give us 4.3 V, which is still well above the spec of 3 V.

The amplifier is driving a 47k load. Rc sets the amplifier output impedance at around 3.3k (the transistor is a high impedance current source, to first order), so we have less than 10% loss of swing into the load, we are still well above our minimum 3 V +ve swing.

To get our total 9 V swing target, we want no more than 2 V across Re, so that we don't have to use a transistor VCE of less than 1 V (rule of thumb to stay linear).

That leaves 2 V across Re at 1.3 mA, so Re = 2.0/1.3m = 1.53k, for which the nearest E12 is 1.5k. It's nice to have a reasonable voltage across Re, for bias stability with temperature. Once you get to less than 1 V across Re (another rule of thumb), the emitter current changes quite a lot with changing temperature, due to temperature dependent VBE. With 2 V on Re, I can pretty much ignore whether the typical VBE for that transistor is really 700 mV or 600 mV at our 1.3 mA collector current.

Bias

As the transistor has a gain of 400 (+/- the 20% from the question gives a minimum gain of 320, but I don't think the question is being conservative enough here, I usually reckon a factor of 2 on beta, so 200 minimum), a ratio of 10% in the bias chain is now seen to be so big that to first order we can ignore the base current taken by the transistor. We can consider it later on if we want to justify that omission.

To set 2 V across Re, we need 2.7 V (nominally) across Rb2, at 130 uA. Rb2 = 2.7/130u = 20.7k. Rb1 = 9.3/130u = 71.5k. The nearest E12s keeping the right sort of ratio is 18k and 68k, or 22k and 82k.

I'll leave it to you to work out exactly what base voltage gets delivered to the transistor when Rb1 and Rb2 take these values, with the transistor drawing a base current of 1.3 mA / 200 (worst case beta), or 1.3 mA / 800 (best case beta).

Gain

With Re and Rc being 1.5k and 3.3k respectively, the gain is in the ballpark of 2, from their ratio. We usually want to be able to increase the gain, so often put a smaller resistor, in series with a capacitor so that it doesn't disturb our DC conditions, across Re as well, to increase the gain.

I'm not sure how you plucked Ve being -5 V, or Ic being 1.09 mA, out of thin air, showing your workings or assumptions would have been good.

This argument above is very much a 'back of envelope' design, which is why I have ignored pretty much any accuracy beyond the first significant figure. A design like this should still work even with large deviations from nominal, with temperature, supply voltage, resistor tolerance or transistor batch variations all upsetting the typical operating point.

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  • \$\begingroup\$ Why are the 4.5V across RC? Isn't the output swing suposed to be the values from where the DC part of the VC varies? (4.5V of interval in this case). Could i use a value below 2V for VRE, for example VRE = 1V? Also how do i know the value of VC? I figured Ic = 1.09mA because i equated: (11/10)Ic x 6 - [(11/10)Ic x (-6)] = 14.4mW (14mW with the 20% margin), meaning this that the total power dissipated = power dissipated by both voltage sources. Then i got VE = -5V because i used VRE=1V, and concluded that VE = VRE - 6V = -5V \$\endgroup\$
    – Aleat
    Commented Sep 23, 2023 at 22:44
  • \$\begingroup\$ @Aleat 4.5 V across Rc? To get nominally + 4.5 V available swing from the quiescent point. Your spec was >3 V, with some margin. There's room for 4.5 V, so that's what I went for. \$\endgroup\$
    – Neil_UK
    Commented Sep 24, 2023 at 5:37
  • \$\begingroup\$ @Aleat Could i use a value below 2V for VRE, for example VRE = 1V? Yes, read my Output Swing section. As you go below 1 V, the bias current becomes more sensitive to changes in values that will happen, resistor tolerance and beta as initial errors, temperature as a 'run-time' error. \$\endgroup\$
    – Neil_UK
    Commented Sep 24, 2023 at 5:39
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    \$\begingroup\$ @Aleat not being a pain anywhere. It's through precisely this back and forth that we might understand where you're stuck, and maybe get you out of it. A transistor collector behaves as a current source, and the Rc sets the output impedance, and the quiescent operating point. You need to be able to swing +/- 3 V from quiescent. So we need at least 3 V across Rc, so that as IC goes down, the voltage is able to rise by at least +3 V. And we need the emitter at least 3V below quiescent, so as IC increases, the output voltage can fall enough. Keep asking if stuck. \$\endgroup\$
    – Neil_UK
    Commented Sep 24, 2023 at 12:50
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    \$\begingroup\$ @Aleat the collector current x Rc sets the quiescent point, VCE has nothing to do with it. Why does TR behave as current source? Physics. It just does. Further explanations beyond the scope of this question, they lie in semiconductor physics. For your purposes, a transistor collector is a current source. 3V on Rc is not quite enough to guarrantee a +3 V swing at the output, we need 20% more, I went for 50% more with my 4.5 V, as there was enough voltage from the power supplies. VE has to be low enough to swing below quiescent without bottoming the transistor (getting VCE too close to 0 V). \$\endgroup\$
    – Neil_UK
    Commented Sep 24, 2023 at 15:49
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You are almost near the solution.

enter image description here

Or this

enter image description here

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  • \$\begingroup\$ I don't understand where you got all those values from \$\endgroup\$
    – Aleat
    Commented Sep 23, 2023 at 17:52
  • \$\begingroup\$ A simulator can answer most questions. You need to use it with some "directives". \$\endgroup\$
    – Antonio51
    Commented Sep 23, 2023 at 19:57

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