How to calculate the via fence spacing between two differential CPWG?

Question

I designed a very compact 4 layer PCB that has many PCIe 2.0 differential pairs spaced in close proximity. In addition to the internal ground planes, I want to fill the signal layers with copper, and have vias between the pairs to serve as ground stitching and fencing.

I want to calculate what the spacing between the stiching vias should be (marked as d on the screenshot). Here are the steps I took to try and solve this:

1. Found this formula to calculate the "approximate highest significant sine wave frequency component" of a square wave signal: $$BW [GHz] \approx \frac{0.35}{Trise [ns]}$$ Assuming a minimum allowable rise time of 50 ps for PCIe 2.0, the result is: $$BW [GHz] \approx \frac{0.35}{0.05 [ns]} = 7 [GHz]$$
2. Calculated the wavelength of said frequency: $$\lambda = \frac{c}{7 [GHz]} \approx 42.83 [mm]$$
3. Calculated the microstrip effective dielectric constant for Er = 4.4 as given by my pcb manufacturer for the prepreg material: $$Er_{eff} \approx 0.64 Er + 0.36 = 0.64 \times 4.4 + 0.36 = 3.176$$
4. Divided the said wavelength by the square root of Ereff: $$\frac{42.83 [mm]}{\sqrt{3.176}} \approx 24.03 [mm]$$
5. Divided the last result (how do I even call it?) by 8, as the "common rule of thumb" found on google suggests: $$d = \frac{24.03 [mm]}{8} \approx 3 [mm]$$

Is this the correct approach?

Answer 1

Yes.

Note that the lowest mode supported is 1/2 λ, so the signals being some margin below that point (for given spacing) is adequate.

The spacing between pair and coplanar ground can also be increased, reducing coupling to the fence in the first place. (I'm guessing the whole point of using it, was to get better isolation between pairs for less space between them, so the picture is more representative than to-scale?)