I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so?
Currently I have the following SystemVerilog implementation
case (bcdIn) 4'd0: muxOut = optionA; 4'd1: muxOut = optionB; 4'd2: muxOut = optionC; 4'd3: muxOut = optionD; 4'd4: muxOut = optionE; 4'd5: muxOut = optionF; 4'd6: muxOut = optionG; 4'd7: muxOut = optionH; 4'd8: muxOut = optionI; 4'd9: muxOut = optionJ; default: muxOut = 'x; endcase
muxOut and each of the "options" are 164 bits wide. The timing report for this snippet reveals a huge delay due to the fanout of the select lines (the digits of bcdIn).
Is there a more efficient way of selecting between large buses? Perhaps a tree construct of MUXes of some sort?
I am willing to code this by hand using
assign statements and the like, but if there's a way to infer faster logic using
case, I'm all ears.