I have been playing with it some, and it is an interesting technology. Your OpenCL kernel gets instantiated as hardware, into a "sandbox" that is surrounded by PCIe and Memory. An optimum kernel for their flavor of OpenCL is heavily pipelined, because that is where FPGAs shine. There are options for vectorization as well as replication, loop unrolling etc. also.
Downsides: Very few FPGA development boards support OpenCL at this time, and they tend to be pretty pricey (think $5k). Compilation takes many hours (hey, it's an FPGA!) and you need a BIG machine in terms of RAM. They recommend a minimum of 24GB, but for anything that is more than hello, world\n, I would make sure you have 64GB at the very least. Not sure how much the licenses are, but as you are talking Stratix V parts and a separate license for the OpenCL SDK, it's certainly not free.
The way all this works is that the compiler (which is LLVM-based like most of the other OpenCL compilers) compiles your OpenCL kernel into an LLVM IR (Intermediate Representation), then an Altera tool generates Verilog from that. The Verilog instantiation of the kernel is embedded into a Qsys system for the other interfaces (board-dependent, mostly PCIe and RAM, clocks and resets, based on Avalon components). Then it grinds all this through the Quartus tool chain to make a bitfile, which is then wrapped into an AOCX file for easy consumption by an OpenCL host. This will take hours.
You can run this whole thing without knowing anything about FPGAs, which is pretty cool. To get something to work is easy, but how easy is it to build something that performs well? I don't know, still learning. There is an interesting optimization guide available here.
Overall, the technology definitely has a lot of potential, but it still feels somewhat bleeding edge (as of Quartus 13.1).
