I am currently taking a university course about computer architecture in which we learned basic DRAM architecture and addressing. As far as I know, each latch is selected using decoder outputs to enable reading or writing. If one decoder is only used for this job, then we would have many AND gates and fan-out. Refer to the figure for an example.
To solve this problem, we used two decoders for selection, which reduced the fan-out (and the number of AND gates supposedly although I am not convinced). Refer to the figure for an example.
My question is, since increasing the number of address decoders seems to reduce the fan-out, why don't we go for 3 or more decoders?
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You can to 3D with memory.
Now you show 8x8 memory cells in X & Y directions. You could make 8x8x8 in XYZ directions.
No one is making silicon that way. We simply can't make silicon that thick. Heat will be a problem.
Take your 8X8 memory IC and put 8 of those on a PCB. Now you have the 8x8x8 you want. Now put 8 of those PCBs in a computer and you have 8x8x8x8. There is no limit.