I've come across a circuit behavior that I find surprising and don't really know how to go about researching it further except just to ask here:

I am building a circuit that needs a momentary RESET signal at the beginning of a longer cycle of user-triggered behavior. The rising edge of the GATE signal through Q2 causes the voltage across C10 to drop briefly, which triggers an astable 555 circuit to express RESET high for a few microseconds regardless of how long GATE is held high (assuming that's longer than the 6us RESET signal):

The rising edge of GATE causes Q2 to briefly short out a capacitor, triggering the 555 timer's astable output

GATE is itself the output of a CD4011B NAND2 element (not shown), which has a fairly weak drive voltage (3.4mA min, 6.8mA typ), but I chose this logic family because it supports 0-12V operation and the rest of the circuit is analog.

I have been under the impression that it's good form to put a resistor between a CMOS output and a MOSFET gate to protect the CMOS from inrush currents, but don't have a good sense for what's an appropriate value. (I've seen some examples where R is very low, 4.7 or 10 ohms; but this would clearly exceed the max drive current and thus cause a very slow rise time.) So I built the circuit on a breadboard and plugged in a handful of resistors in turn (22, 100, 470, 1k, 1k2, 4k7, 10k), measuring the effect of resistance on the rise time of GATE and the fall time of GATEDN with my 'scope:

GATEDN's fall time scales pretty linearly with 1/R, which makes sense; R=22 ohms allows a 6ns pulldown time, whereas 10kOhm extends it to 87ns. Values of R through 1.2kOhm cause the rise time of GATE to hover around 45ns; stiffer impedance like 4.7k or 10k allow a sharper rise time of ~25ns....

Except 1.0kOhm. This causes GATEDN's t_fall to be 15ns, slightly faster than 1.2kOhm (16ns) and almost ~2x the duration of 470 ohm (9ns) as expected. But this resistor seems to have hit a "sweet spot" where I measure a GATE t_rise of 27--31ns, faster than any other low-valued resistor enables, without sacrificing transistor turn-on time.

I would have expected resistors above ~2.2kOhm to have fast output rising edges, then as the current drive of the CMOS gate is exceeded, for the speed to slow down proportional to the Iout=Vcc/R rule. What makes 1k an exception?

If it makes a difference, this was measured through a 10:1 200MHz probe (18pF || 10MOhm).

  • \$\begingroup\$ What is your Vcc? \$\endgroup\$
    – CL.
    Commented Oct 3, 2023 at 12:42
  • \$\begingroup\$ That sounds well within measurement error. Did the scale/axis change at any point between measurements? Did you measure the resistors, are they accurately the values they say they are? Plotted on a graph, do the data follow the expected curve plus or minus some random error, or are there outliers, or is there a systematic trend outside of your expectation? \$\endgroup\$ Commented Oct 3, 2023 at 16:13
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    \$\begingroup\$ @CL. Vcc is 12V \$\endgroup\$ Commented Oct 4, 2023 at 3:14
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    \$\begingroup\$ @TimWilliams Scale/axis kept fixed. Repeated measurements of rise times varied +/-3ns for each resistor; e.g. 470R would consistently get 42--45ns rise times. The 1k resistor was a distinct outlier at 27--31ns; I never saw other low-value resistors in the 30's of ns. The "1kOhm 5%" resistor measures 993.4 ohm on Agilent 34401A via 2-wire ohms reading. "470R" measures 470.6 ohms. They're all within 2% of spec. \$\endgroup\$ Commented Oct 4, 2023 at 3:23

2 Answers 2


The rise time of the GATE is entirely determined by the loading effects that both the resistor R11 and the gate capacity \$C_{G_\text{Q2}}\$ of Q2 (in short called the load impedance \$Z_{G_\text{Q2}}\$ below) exert on the output stage of the CD4011B, shown below (and excerpted from TI CD4011B datasheet p. 3-28) for the sake of completeness

enter image description here

Said this, there are two major phenomena you should be aware of when coupling such a stage with any kind of output load.

  1. If the resistive component R11 of load impedance is low respect to the charging \$p\$-channel transistor drain-source resistance \$r_{DS}\$, the rise of the GATE signal is limited by the maximum \$I_\text{out}\$ and the by the value of the gate capacitance since, as you noted in the OP. From the equivalent circuit point of view you have the following situation


simulate this circuit – Schematic created using CircuitLab
In this case the rise time \$t_r\$ is strictly higher than the charging time of the gate capacitance \$C_{G_\text{Q2}}\$, i.e. $$ t_r > \frac{V_\text{CC+}}{C_{G_\text{Q2}}\cdot I_\text{out}} $$ Increasing R11 from these low values towards \$r_{DS}\$ will decrease the rise time of the GATE signal. However

  1. When the resistive component R11 of the output impedance is high, the rise of the GATE signal is slowed down by the Miller effect which arises on the output stage of the CD4011B. This happens because the have a couple of complementary symmetry common source amplifiers whose small signal gain rises in a nearly proportional way to the rising of R11: an equivalent circuit is shown here below


simulate this circuit

In this case the last two stages act as an integrator, thus the output of the CD4011B can rise again only in a limited way, determined by the \$r_{DS}\$ of the discharging inner \$n\$-channel transistor and by the Miller capacitance \$C_\text{Miller}\$.

Said that, as the rise time \$t_r\$ of the GATE signal increases for values of R11 increasing towards \$\infty\$ or decreasing towards \$0\$, by continuity it should have a minimum value, and in your circuit it seems that $$ \mathrm{R11}_{t_{r_\min}}\simeq 1\mathrm{k}\Omega $$ due to the very particular characteristics of the components you employed in the construction of your circuit.

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    \$\begingroup\$ @daniele-tampiere got it, that makes a lot of sense. Thanks! When you write "due to the very particular characteristics of the components you employed in the construction of your circuit" does that mean a different CD4011B might experience this minimum rise time with a different Rmin? Should I leave it at 1k and expect this performance on a PCBA? Or would it vary lot-to-lot? \$\endgroup\$ Commented Oct 4, 2023 at 3:32
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    \$\begingroup\$ @AaronKimball exactly: I expect that the value of the R11 resistance for which the GATE signal reach a minimum \$t_r\$ would vary from lot to lot. However I expect also that the range of these values will be at most the within \$\pm 33\%\$ of the value you found, and the mean value to be near that one. This is simply due to the normal range of tolerances experienced with semiconductor components, something we have to comply with every day, so I'd leave the experimental value you found and possibly change it only if strictly needed after a normal lot testing. \$\endgroup\$ Commented Oct 4, 2023 at 4:38
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    \$\begingroup\$ Note also that the parameters of Q2 influence the Rmin value of R11, but this is not negative as the joint distribution of two or more normally distributed parameters plays a somewhat "spread reduction" rôle. I'd not worry and see what happens on the first engineering lot. \$\endgroup\$ Commented Oct 4, 2023 at 4:43

This question illustrates the pitfalls of reducing complex waveforms to simple metrics. The explanation is obvious when looking at the waveform and circuit itself, but confusing or un-intuitive when considering only the measurement values, or their trend, because those values necessarily discard a majority of the signal's information.

For clarity, I'll refer to the logic output pin and the MOSFET gate pin, as such; I'll only refer to net names in CODE.

Waveform capture before and after resistor

I have set up essentially the circuit and parameters shown, and probed either side of the resistor R11, at a value of 1kΩ. On Ch2, we see the Miller plateau and gradual rise we expect at the MOSFET gate; on Ch3, we see the sharp rise of the logic output, with a slow settling which clearly tracks with the gate voltage.

We can model the logic output as a resistance RDS(on) from VDD or to GND. In this case, during the plateau, gate voltage is about 3V, logic pin 10V, and supply 12.3V. The current then is ((10V) - (3V)) / (1kΩ) = 7mA, and the pull-up strength, ((12.3V) - (10V)) / (7mA) = 329Ω -- a typical value for the CD4000 family at this voltage.

Thus we have an equivalent circuit where a Thevenin square-wave source drives an RC network:


simulate this circuit – Schematic created using CircuitLab

We can't measure the (ideal) voltage itself, only the midpoint between resistances, and thus we measure a mixture of the RC ramp plus source step.

Risetime is calculated simply between fixed thresholds: the steady-state or "top" and "bottom" values of the waveform are found through a histogram method, and the 10 and 90% crossing points are found (which I've illustrated by placing horizontal cursors on the waveform).

This is a very nonlinear threshold process -- it is very sensitive to the exact shape of the waveform, and erroneous values are easily had. For example if the waveform has ringing, do you count the initial rising slope (but only if it crosses 90%?), or should you smooth over short-term transients and look at the overall trend? The real answer cuts across the matter: such messy signals simply shouldn't be measured in this way in the first place. Rise/fall time is a meaningful/useful parameter of well-defined square waves. Square waves are common enough in practice that they're worth having several measurement shortcuts for (rise/fall, high/low voltage and time, frequency, duty, delay, etc.), but we must keep in mind it's a very special case out of all possible signals.

So the sort of meta-answer is: you've moved from one signal where the risetime measurement is meaningful, to one where it is less so. Though, "meaningful" depends on what we're using the measurement for (which, isn't really anything here, this was just a curiosity, right?), and signals like this do show up in a number of practical settings; which may in turn be measured by other methods (for example the eye diagram of signal quality analysis).

If I shift the measurement thresholds to a more lax 20-80% for example, I get 22ns, more or less the expected natural rate of the logic pin. Or if I gate the measurement to just around the leading edge, I get 17.8ns. (The unloaded value is 16.4ns, i.e. for R11 infinite, and whatever 10s of pF loading the probes and breadboard contribute.)

So, the result is a combination of:

  • Measuring midway along a (step source)-R-RC divider
  • Having an RC time constant longer than the logic pin's risetime
  • The arbitrary thresholds used in the measurement, which are representative when the waveform is well-defined, but less useful otherwise.

Note that measuring at the MOSFET gate gives the expected trend, inverse with resistance, when we include the total resistance (RDS(on) plus R11). Which has a minimum of 83ns (R11 = 0), up to 111ns at 220Ω, 157ns at 470Ω, etc.

Which effectively gives us another way to measure RDS(on): risetime about doubles at 470Ω, suggesting the average internal resistance is comparable. This is partly true, but partly skewed by the MOSFET's nonlinear gate capacitance as well, so it's only a rough figure.


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