This question is related to (System/)Verilog HDL simulation for FPGA inside tools like Vivado, Modelsim etc.

In a sample code where I have 2 net type variables, I want to plot a waveform for a conditional statement like this:

if (wire1 & (~wire2)) begin
// Some action

I know I can add wire1 and wire2, but I'd like to make a custom signal for the if condition (wire1 & (~wire2)) and see how it varies with time in Vivado. How do I do it?

I know one way to do this is to create a continuous assignment statement with the same condition and add it to the waveform, but I am curious if there is another simpler, smarter way of doing this?


1 Answer 1


I don't see any way to create a custom signal in the Vivado waveform viewer. I looked in all the usual places in the version that I have installed. I also read through the Vivado documentation online, and I did not see a way to do this (I presume the online version is the most recent).

The tool allows you to do other common waveform operations, such as changing a signal radix and reversing bit order of a bus. But, it does not seem to allow you to create a new signal from a logical expression of other signals.

After you scour the documentation for the version you are using, and you don't find anything useful, I think your best bet is to create a new signal in the Verilog source code, as you mentioned. For example:

wire enable = wire1 & (~wire2);

That extra work will have long-term benefits:

  • You will only have to do it once, instead of every time you want to look at waveforms
  • The code will potentially be easier to understand because you gave the expression a meaningful name
  • If you need this expression elsewhere in the code (as often happens), then you don't need to copy and paste it several times

If you don't want to edit the Verilog code for that module, you could create a new signal in your testbench code and use a hierarchical specifier to scope down into the module from the testbench instead. For example, if you named your design module instance as dut:

wire enable = dut.wire1 & (~dut.wire2);

You should contact the tool vendor and request this feature. I have used another waveform viewer with this capability (the Verdi nWave tool by Synopsys).

  • \$\begingroup\$ By "scoping down" the module, you mean adding extra input signal and assigning it to that expression? \$\endgroup\$
    – lousycoder
    Oct 6, 2023 at 10:11
  • 1
    \$\begingroup\$ @lousycoder: No, I did not mean adding an input port. See my updated answer. \$\endgroup\$
    – toolic
    Oct 6, 2023 at 10:24
  • \$\begingroup\$ That's certainly a better way to create custom signals, so that design is not disturbed. \$\endgroup\$
    – lousycoder
    Oct 7, 2023 at 7:31
  • \$\begingroup\$ there are two ways of specifying assertions in SystemVerilog, either declaratively (outside of any procedural block, may be in a tb file) or directly within the procedural code, can the method of "scoping down" be used to declare (concurrent) assertions inside a testbench that relate to some regs in a procedural block somewhere down inside some module in the design hierarchy? \$\endgroup\$
    – lousycoder
    Jan 31 at 1:53

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