My textbook (Brown and Vranesic) gives the following code for a simple 4-bit RCA implementation in Verilog:

// 4-bit ripple-carry adder
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout); 
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;

fulladd stage0 (carryin, x0, y0, s0, c1); 
fulladd stage1 (c1, x1, y1, s1, c2); 
fulladd stage2 (c2, x2, y2, s2, c3); 
fulladd stage3 (c3, x3, y3, s3, carryout);


// Full-adder
module fulladd (Cin, x, y, s, Cout); 
input Cin, x, y;
output s, Cout;

assign s = x + y + Cin;
assign Cout=(x&y)|(x&Cin)|(y&Cin);


My question is about why there is no need for a

wire c1,c2,c3;

statement given that these signals are not declared as inputs or outputs. Is this an error? I ask because in a future example they do seem to use a wire statement for the equivalent signals (this time expressed as bits of a vectored signal).


2 Answers 2


Is this an error?

This is not an error. Declaring these signals is optional. Refer to IEEE Std 1800-2017, section 6.10 Implicit declarations:

If an identifier is used in the terminal list of a primitive instance or in the port connection list of a module, interface, program, or static checker instance (but not a procedural checker instance, see 17.3), and that identifier has not been declared previously in the scope where the instantiation appears or in any scope whose declarations can be directly referenced from the scope where the instantiation appears (see 23.9), then an implicit scalar net of default net type shall be assumed.

In your code, the signals are in the port connection list of a module.

It is important to note the word scalar. That means all implicit signals will be 1-bit wide. It is a common mistake to connect an implicit signal to a module port which is multiple bits wide, like an 8-bit data bus. In that case, you might see a compile warning about a signal width mismatch. If you want to avoid the warning, then you need to explicitly declare the signal with the width that matches the width of the module port, which is why the book's other example shows the wire declaration.

There are other circumstances where the signals need not be explicitly declared as well.


Because in many(but not all) tools, an undeclared net is implicitly a wire. Generally considered poor practice to not declare them though.

  • \$\begingroup\$ The syntax is allowed in all tools that comply with the Verilog IEEE Std. \$\endgroup\$
    – toolic
    Oct 3 at 15:32

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