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In my module I am taking two input 8-bits.

mymodule(input clk, input [7:0] AS_1,input [7:0] AS_2, output [7:0] AS)

Now I want to create a container that will keep both inputs, I mean I want to join them in a single one. I want to do something like that:

reg [15:0] JOIN = AS_1 and AS_2 ---> all their bits should be arranged in a single container

But I don't know whether it should be a reg type or wire or something else, because I'll need to make other operations with that JOIN

Any help, advise or suggestion would be highly appreciated!!!

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2 Answers 2

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wire [15:0] joined;
assign joined = {AS_1, AS_2};

That creates a wire which always has the joined value.

The braces can be used in most places to concatenate values like this.

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  • \$\begingroup\$ ok but the point is that if I had to do something like this joined = joined & 8'b11110000; statement would it work? \$\endgroup\$
    – Bledi Boss
    May 6, 2013 at 21:58
  • \$\begingroup\$ @BlediBoss I think that might be a combinatorial loop depending on how you write it, why not have joined_masked = joined & mask. \$\endgroup\$ May 6, 2013 at 22:17
  • \$\begingroup\$ @BlediBoss - pre_randomize above is correct, generally in Verilog it's best to adopt a style where every variable is assigned to in only one place. Whether you want reg or wire, and assign versus "<=" in an always block, is determined by what else you want to do and whether you want it immediate or on a clock edge. \$\endgroup\$
    – pjc50
    May 7, 2013 at 11:09
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If you wish to do additional calculations to JOIN I would recommend the following:

reg [15:0] JOIN;
always @* begin
  JOIN = {AS_1,AS_2};
  JOIN[8:0] = JOIN[8:0] & mask;
  // ... other code
end

If your simulator supports SystemVerilog, I will recommend you use logic instead of reg. Technically the two are the same, however for readability it is best to use reg for intended flops and logic for intended combination values.

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  • \$\begingroup\$ AS I can see you are defining JOIN as a single bit, and assigning later as if it was 8 bit.! But it is supposed to be 16 bits. \$\endgroup\$
    – Bledi Boss
    May 6, 2013 at 22:25
  • \$\begingroup\$ @BlediBoss, good catch. It was a typo. I updated it to a 16 bit bus. \$\endgroup\$
    – Greg
    May 6, 2013 at 22:50

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