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I am working on 4-layer PCB with following stack-up:

  • Layer-1 Signal traces
  • Layer-2 Ground
  • Layer-3 Ground
  • Layer-4 Signal + Power traces

The PCB contains ESP32-S2 MCU with USB and chip antenna. I am going to use JLC PCB for manufacturing with this impedance controlled stack-up (1 mm PCB thickness). enter image description here

I have calculated required trace width to get 50 ohm impedance for RF trace and 90 ohm diff. impedance for USB lines.

According to the hardware guidelines provided by Espressif Systems, It requires unbroken ground plane under both these impedance controlled traces. I have Unbroken ground planes in layer 2 and layer 3, but not in layer 4.

Is it okay to have signal or power traces under impedance controlled traces in layer 4 as shown in both these images below? (Check red marked area in layer 4)

Antenna

enter image description here

USB

enter image description here

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1 Answer 1

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Yes, it is only important to have unbroken ground in the immediate reference plane.

This is L2 in your case.

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    \$\begingroup\$ Essentially, the ground plane shields the controlled-impedance traces from anything happening on the other side of it. You can run whatever noisy signals you want on the back side, and as long as the ground plane is good enough, microstrip on the front side won't see any of it. \$\endgroup\$
    – Hearth
    Oct 4 at 14:57
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    \$\begingroup\$ Well, not any, there are limits. The limits are given by the attenuation rate of the foil thickness (look up copper shielding effectiveness) and the relevant frequencies and required isolation between said traces. If the receiver is immune to ~kHz noise for example, it might be fine to run a power switching trace through such a location; but if that disturbs the receiver's biasing, introduces IMD, etc., it would be a poor choice. \$\endgroup\$
    – Tim Williams
    Oct 4 at 15:16

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