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Consider this circuit:

enter image description here

The capacitances \$C_1\$ and \$C_2\$ are chosen so that the AC current at this frequency will pass through with negligible impedance, while DC current must pass through all the resistances.

The Zener diode is an ideal Zener diode; when operating in the breakdown region, it has a voltage of $$V_z = V_{z0} + r_z I_z$$, where \$V_{Z0} = 10 \$ V and \$r_z = 0\$. Of course, \$V_z\$ and \$I_z\$ follow the convention from Sedra:

enter image description here

Here's what I have figured out:

  1. When the source voltages, \$V_s = 16 + 14 \sin t \$ , is below \$V_{z0}\$, then the output voltage equals the input voltage \$V_0\$. That is, when \$V_s < 10 \$ V, then \$V_0 = V_s\$.

  2. When the AC source is removed, then the output voltage is given by: $$V_0 = V_{z0} + r_z \frac{16 - V_{z0} }{ 2k + 1k + 1k } = 11.5 \text{ V} $$

I'm temped to think that this is the whole solutions - that $$ V_0 = \begin{cases} V_s & \text{if } V_s < V_{z0} \\ 11.5 \text{ V} & \text{if } V_s \geq V_{z0} \end{cases}$$

However, the presence of a discontinuity at \$V_s = V_0\$ seems incorrect. Any suggestions? What is the output voltage for this circuit?

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  • \$\begingroup\$ You've written $\sin t$ with no $\omega$, so your frequency is very low and the capacitance will be an awkward value. Is this what you intended? \$\endgroup\$
    – Reinderien
    Commented Oct 8, 2023 at 14:59
  • \$\begingroup\$ For this circuit, you have to do to full large signal analysis. Are you sure that Vsin =14V is not a mistake? Because if Vsin is 14V then this is not an easy exercise. \$\endgroup\$
    – G36
    Commented Oct 8, 2023 at 15:10
  • \$\begingroup\$ @G36 Yes, this is a large signal analysis. That's the challenge. \$\endgroup\$ Commented Oct 8, 2023 at 15:51
  • \$\begingroup\$ @Reinderien This is a theoretical exercise. You can change \$\omega\$ to be larger, if you want. \$\endgroup\$ Commented Oct 8, 2023 at 15:51

1 Answer 1

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The DC source imposes a current of 1.5 mA through the loop. This creates a DC voltage of 3 V across C1 and 1.5 V across C2. This effectively turns these capacitors into additional voltage sources, which vastly simplifies the analysis. The two branches of this circuit produce identical outputs, at least initially. The asymmetric nature of the AC current through the diode causes a slight shift in the capacitor voltages over the long term.

schematic

simulate this circuit – Schematic created using CircuitLab

EDIT: I've been playing around with this simulation some more. I switched to truly ideal diode models, and reduced the capacitor values to decrease the setting (simulation) time to a reasonable value.

It turns out that the voltage across C1 rises to 4.9 V and the voltage across C2 rises to 2.7 V. This means that the corresponding currents in R1 and R3 rise to 2.45 mA and 2.70 mA, respectively. I suspect that this is due to the asymmetric current flow in the circuit, but I'm still scratching my head over how to work out these values analytically.

schematic

simulate this circuit

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  • \$\begingroup\$ But it looks like the diode will be forward-biased for Vsin < -11.5V. \$\endgroup\$
    – G36
    Commented Oct 8, 2023 at 15:55
  • \$\begingroup\$ @G36: Yes, the diode does get forward biased during part of the cycle. \$\endgroup\$
    – Dave Tweed
    Commented Oct 8, 2023 at 16:01
  • \$\begingroup\$ This won't move the average capacitor voltage? \$\endgroup\$
    – G36
    Commented Oct 8, 2023 at 16:05
  • \$\begingroup\$ @G36: Yes, I said that. Working out the amount of that shift is a bit more complicated. \$\endgroup\$
    – Dave Tweed
    Commented Oct 8, 2023 at 16:06
  • \$\begingroup\$ Ok I see. Stupid me, I looked only at the circuit diagram and did not read the whole answer. \$\endgroup\$
    – G36
    Commented Oct 8, 2023 at 16:12

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