So I was checking out sequential logic and I found two different circuits for flip flops (or latches, or both). Let's take D flip flop for my quesiton.

There's one circuit here, showing a D flip flop:

enter image description here

I found an issue here. Flip flops are meant to be edge triggered by clock. But here, suppose the clock is high, and the input changes during positive half cycle (let's say halfway). If Data changes, won't that reflect in the output immediately? There's really nothing stopping the output from changing.

One more important thing is that there's many places where this is called Gated D latch.

Another circuit:

enter image description here

This one is called Master Slave D Flip flop. What it basically does is:

  1. During negative cycle, master is enabled by clock, storing data.
  2. At the positive edge (transition), slave takes the input and propagates it to Q.
  3. Even if any changes in D occur during the positive half, nothing is reflected in Q.

Technically, isn't this what a flip flop is supposed to be? Edge triggered? Admittedly, it is a bigger circuit and is more cumbersome wrt design, area and number of gates & transistors. But the operation is as it should be (edge triggered)

Why do so many textbooks and online resources call the upper circuit a Flip Flop, when it basically works as a latch? Is there something that I am missing here?


2 Answers 2


Unfortunately, there is a great deal of confusing usage out there. Many people, myself included would describe an edge triggered memory element, and only an edge triggered memory element as a flip-flop. And a level triggered element as a latch. Under that definition, the both circuits in your question is not as flip-flop but as latchs. However, I am unable to enforce my preferred definition, so you will see that circuit sometimes called a flip-flop.

The 2nd circuit is a master-slave latch. But if the symbols used were slightly different, it would be a flip-flop.


simulate this circuit – Schematic created using CircuitLab

Note the little triangle next to the CLK inputs. This signifies edge triggering, and the edge triggering makes the above circuit a master-slave flip-flop.

The master-slave latch and the master slave flip-flop have different behaviors.

The master-slave flip-flop records the value of the data line on the rising (alternatively falling) edge of the clock, and then presents it to the output on the falling (alternatively rising) edge of the clock.

If the data input does not change while the clock is high (or alternatively low) then the behavior of the master-slave latch is the same as that of the master-slave flip-flop.

However, the input buffer of a master-slave latch is transparent to changes in the input while the clock is enabled. That is, if the data input changes while the clock is high (alternatively low) a master-slave latch will record that change in its input latch, and will transmit that new value to the output latch when when the clock goes low (alternatively high) provided the data has been stable long enough before the clock going low, and remains stable for long enough after the clock goes low.

  • 1
    \$\begingroup\$ I understand why my first circuit is not flip flop. But, why the second one though? The end result is basically similar to what your circuit does. The only change is WHEN the data storage and transfer occurs, isn't it? In your case, data is stored during posedge and propagated in negedge. \$\endgroup\$
    – DaveFenner
    Oct 8, 2023 at 19:25
  • \$\begingroup\$ @MaheshNamboodiri see my addition to my answer. No the two circuits have identical behavior in some circumstances, but in the general case, their behaviors are different. \$\endgroup\$ Oct 8, 2023 at 19:56
  • 2
    \$\begingroup\$ > However, I am unable to enforce my preferred definition Most eloquently phrased! \$\endgroup\$
    – noughtnaut
    Oct 9, 2023 at 9:35
  • \$\begingroup\$ Echoing @MaheshNamboodiri point, your circuit isn't a flip-flop whereas his is. And his is the basis of flip-flops in FPGAs and ASICs to implement each register. So you're mistaken about yours, I'm afraid. \$\endgroup\$
    – TonyM
    Oct 9, 2023 at 15:59
  • \$\begingroup\$ @TonyM in what way is my circuit not a flip-flop? Also, are you claiming that FPGA's and ASIC's implement registers is not with edge triggered flip-flops, but with MaheshNamboodiri's circuit? \$\endgroup\$ Oct 9, 2023 at 22:59

This is intended as an answer to the terminology question.

Why do so many textbooks and online resources call the upper circuit a Flip Flop, when it basically works as a latch?

Because different authors use the words in different ways.

Some authors prefer a narrower meaning for "flip-flop" (edge-triggered) and some use a wider one (all bistables). Caveat lector!

The standard text The Art of Electronics, 3. ed, Horowitz and Hill, CUP 2020, uses "flip-flop" in the wider way for any kind of bistable circuit built on crossed-negation. They give its simplest form as: enter image description here
From H+H, Fig. 10.49.

They specify SR, JK, type-T, D, clocked, master-slave, edge-triggered, as appropriate for the specific kind. The largest has ten gates.

Your first circuit is described (in section 10.4.2, without R=~S) as a "clocked flip-flop", but note:

It’s also known as a transparent latch: the output “sees through” to the input when the clock is HIGH.

They continue with the definition of latches but note it is ambiguous. Emphasis added:

10.5.1 Latches and Registers
A set of set of individual D flip-flops constitutes a register, but it has more inputs and outputs than necessary. Because you don't need separate clocks, or SET or CLEAR inputs, those lines can be tied together.
The term "latch" is usual reserved for a special kind of register: one in which the outputs follow the inputs when enabled, and hold the last value when disabled. But the term "latch" has become ambiguous with use, so the terms "transparent latch" and "type-D register" are often used to distinguish these closely related devices. As an example, the 573 is the octal transparent latch analogous to the 574 D register, complete with three-state outputs.


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