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Background

I have been considering using the VOM1271 photovoltaic gate driver with an N-channel mosfet to do simple on/off (no PWM) high-side switching of circuits up to 84V (previous question for context - optional).

The VOM data sheet states 53us turn on and 65us turn off times. However, this is only with a 200pF gate capacitance whereas most power mosfets with low Rds(on) can be up to 10nF as a reasonable upper bound, so the times would likely proportionally increase with the gate capacitance. Also, those times assume an LED forward current of 20mA, whereas I would like to use 5mA if possible to save power, as I am only switching occasionally. At 5ma the stated turn on time increases to around 160us, but the turn off time decreases to around 40us. So, for a 10nF gate capacitance with 5mA forward current, I would expect about 8ms turn on and 2ms turn off times with this gate driver.

However, the datasheet also shows that this turn on time includes the propagation delay from the start rise of the input signal to the start of the rise of the output voltage, so the actual rise time that the gate voltage spends going from 0% to 90% is likely less than 8ms.

I was aware that during the mosfet turn on period, it has to transition through a sort of half-on half-off state, and during this transition time, the mosfet can have a large transient spike in power due to the simultaneous medium Vds and medium Id.

To confirm this behaviour, I did a simple simulation on falstad.com, where I modelled the VOM as a 5V voltage source and 1MΩ resistor, based on the worst-case voltage of 5V and short circuit current of 5uA when If=5ma and Ta=100C. I used an 84Ω (minus 5.2mΩ for the mosfet's Rds(on)) resistive load to simulate drawing 1A from the 84V supply when the mosfet is fully on, as this is about the max current one of my loads would be drawing in my system.

Simulation Circuit Diagram

The results confirm the large spike in power that lasts for about 0.6ms and peaks at a maximum of 21W (as opposed to the steady state value of 5.2mW), although I don't think the duration and max value are necessarily 100% accurate, so I'm mainly just confirming that the spike happens as expected. Simulation Results Graphs From Left to Right: Gate Capacitor, Mosfet, Load

Voltage=Green, Current=Yellow, Power=Grey

From the simulation it also shows what region the mosfet is operating in at the current time step. First, as Vgs is rising from 0V to 5V, the mosfet first goes from cutoff region (off), to saturation region once just above the threshold gate voltage (Vth), to finally linear/ohmic region once at a certain additional voltage margin above Vth. It is during the saturation region period that the power spike occurs.

Question

Although this power spike occurs, you can see that it does not last for very long, so the total energy/heat generated in the mosfet is much smaller than if that same peak power occurred continuously/during steady state.

Therefore, I did some research to try to figure out how to calculate the maximum acceptable turn on/off time period that wouldn't overheat the mosfet. This includes articles from Analog Devices, Texas Instruments 1 & 2, and Homemade Circuits.

  • From the AD article, it mentioned that for events under 10ms, the case temperature of the mosfet does not increase significantly, so Tc can be taken to be the same all the way through the transient event.
  • In addition, the AD article mentioned one method of using the transient thermal impedance graph on the datasheet along with the power of the pulse to determine if Tj will rise above the safe limit (usually 150-175C), which is valid for moderate Vds values (i.e. not in thermal instability/"Spirito" region).
  • Similarly, all of the articles talk about how the Safe Operating Area (SOA) graph on the datasheet can be used to determine if a certain combination of Vds and Id is safe for the mosfet with different pulse lengths from 100us to DC.

The problem I had with either the thermal impedance or the SOA methods is that in all the articles I could find so far, they talk about using a combination of a given constant Vds with a constant Ids over the whole duration of the pulse. However, for the turn on behaviour I described before, both Vds and Id are constantly changing over the course of the pulse from Vds=84V,Id=0A at the start, to Vds=Almost 0V,Id=1A at the end.

  • So then how is it possible to use those start and end points and the approximate turn on time of less than 8ms to infer if the behaviour is safe?
  • And if I plot those two points on the SOA graph, how should I connect them, because it may not be just a straight line/linear transition between the two?
  • And then once a line is drawn, which of the timed pulse lines would you compare it against to make sure that it is safe? The 10ms line since the total period is about 8ms? But already from the simulation it appears that the mosfet is passing through the saturation/high power region for much less than the whole 8ms, even if it takes 8ms to reach 90% of max Vgs...

So it seems a bit confusing to try and use the SOA to determine if the behaviour is safe or not. So my question is:

How can you use the SOA or anything else on the datasheet to calculate the maximum acceptable duration for the turn on/off period so as not to heat up the mosfet by any significant amount and so keep it safe? Or is it not possible to use only the datasheet for this kind of complex varying behaviour, and some data from an accompanying simulation is mandatory?

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  • \$\begingroup\$ It is possible to model the Tj of the device itself. If a transient thermal impedance model is not provided from the manufacturer, it can be derived from the impedance plot, with some fiddling. See: electronics.stackexchange.com/questions/682875/… \$\endgroup\$ Oct 9, 2023 at 21:59
  • \$\begingroup\$ What FET you are using? Is there a way you can feed 20ma (or even 40ma) to the LED for a second (or less), then switch to 5ma to save power? Maybe you can pull it from drain... If you can, I think that would "flatten the curve" to well within the SOA. You could also use a 2nd open-drain opto to turn it off faster and help the smaller problem you're facing. \$\endgroup\$
    – dandavis
    Oct 9, 2023 at 22:01
  • \$\begingroup\$ @TimWilliams I'm not sure if a thermal model is provided for some of the mosfets I was looking at, but if it was, what program would I use to use the model? I'm a novice when it comes to simulation so that's why I mentioned trying to use the datasheet first in order to do some kind of direct calculation knowing only duration=8ms, off-voltage=84V, on current=1A \$\endgroup\$
    – ScottyN91
    Oct 9, 2023 at 22:27
  • \$\begingroup\$ @dandavis I was originally looking at using the IRLU3110Z since it is through hole, but I've since switched to considering surface mount as well as well as I will need to design a PCB in order to use the VOM gate driver anyway. So looking through JLCPCB's catalogue, APG046N01G seemed suitable, since my main requirements for the mosfet are Vds limit>84V and low rds(on) at 5V Vgs. It's possible that I could use two different IO pins from the ESP32 to turn on two different paths, one that has a low value resistor for 20mA+, and the other that has a higher value resistor for 5ma. \$\endgroup\$
    – ScottyN91
    Oct 9, 2023 at 22:31
  • \$\begingroup\$ However first I wanted to check if it was necessary to do so by determining the maximum acceptable turn on time. It is worth noting as well that 10nF is sort of a worst case, as I've only seen that in 1 or 2 mosfets I've looked at so far, and both of the two mosfet models I mentioned have 4nF or less input/gate capacitance in reality, but my question is supposed to be generic so I can calculate this on any mosfet, so I gave 10nF as a generic worst case. \$\endgroup\$
    – ScottyN91
    Oct 9, 2023 at 22:33

1 Answer 1

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First note that Safe Operating Area isn't just about power and heat it's about an internal runaway condition caused by spot heating on a die (Vgs treshold lowers at high temps meaning a small part of the die that gets hot may start hogging current when Vgs is near the threshold). This property varies widely between mosfets and actually has gotten worse in many modern mosfets that have been heavily optimized for switching applications.

To answer your specficif question it's always hard to analyze dynamic switching scenarios however a resistive load is relatively simple. I'd plot the operating points and verify they're all under the 10ms line in the SOA.

Vds    Amps
0      1
21     0.75
42     0.5
63     0.25
84     0

See the thermal instability region is where the line tilts downwards. The existence of this inflection (blue), its position and angle all vary widely. enter image description here

Here is a mosfet you suggested in a different question with an extremely steep inflection suggesting 0 amps allowed at high voltages (though strangely the graph ends at 1A) enter image description here

Compare that to this otherwise similar part CSD19533KCS. Note the table from above is marked in blue showing this part is reasonably safe. enter image description here

Some references: https://www.ti.com/lit/an/sluaao2/sluaao2.pdf?ts=1696852204544&ref_url=https%253A%252F%252Fwww.google.com%252F

https://www.analog.com/en/technical-articles/mosfet-safe-operating-area-and-hot-swap-circuits.html

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  • \$\begingroup\$ asdf30 - Hi, Please note the site rule which requires that when a post includes content (e.g. text, image, photo etc.) copied or adapted from elsewhere, that content must be correctly referenced. As a minimum, for online material the source webpage or PDF etc. should be named & linked (see that rule regarding references for books / articles etc.). Therefore please edit your answer to include the required source links for those 3 images. Thanks. \$\endgroup\$
    – SamGibson
    Oct 9, 2023 at 23:06
  • \$\begingroup\$ @asdf30 The method of plotting the operating points seems like a reasonable suggestion, but I have a few questions: 1. Would you say it's erring on the side of caution to use the 10ms line as the limit as you suggested, when the actual rise time from 0% to 90% is less than the 8ms I gave due to subtracting some unknown propagation delay (it's not given in the VOM datasheet), and also because in the basic simulation it suggested that the total time spent in the saturation region is far less than 8ms (maybe even 0.6ms), even if the Vgs rise time from 0% to 90% is around 8ms-propagation delay? \$\endgroup\$
    – ScottyN91
    Oct 9, 2023 at 23:28
  • \$\begingroup\$ Another reason I was unsure about using the 10ms line was, given that voltage and current are not remaining at any those points for the full 10ms, is it still valid to use the SOA graph in this way, or should you use a higher line such as the 1ms line, since each of those points technically has a duration of 0? I'm mainly thinking back to the examples given in the SOA articles that only show it being used with pulses of a fixed Vds and Id. I suppose you could say it would again be erring on the side of caution to say that any of the Vds and Id points are maintained for the full 10ms. \$\endgroup\$
    – ScottyN91
    Oct 9, 2023 at 23:34
  • \$\begingroup\$ 2. If the load is not simply resistive and is a complex circuit such as an LDO, DC-DC converter or USB device, would it be possible to plot the points then, or would you need to do some kind of proper circuit simulation including a thermal model of the mosfet? I suppose a simplification of such a load would be just to assume it to be resistive with the resistor value sized to create the specified maximum current when the full supply voltage is across it (minus a bit of voltage for the Rds(on) of the mosfet), as I did in the simulation? \$\endgroup\$
    – ScottyN91
    Oct 9, 2023 at 23:41
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    \$\begingroup\$ @ScottyN91 It's wise to have margin regarding SOA charts because they're 'typical' and based on 25C numbers. In regards to your question if I knew the fet was spending 10ms in the linear region I'd follow the process above to verify it's safe at any possible operating point for the full 10ms (even though I know its traversing a curve through different points in that time). On the other hand yes I think it's reasonable to use the actual linear region time (0.6ms you say) instead of the entire gate rise time. \$\endgroup\$
    – asdf30
    Nov 24, 2023 at 14:42

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