first let me define glitches as i understand it and correct me if i"am mistaken. glitches are the propagation of unstable signal through the system it happens when one of the operand arrive to computational block(adder for example) before the other operand .
ok , so we use a pipe-lined architecture (putting synchronous registers or latches between every combinatorial block between an adder and a multiplier ) to avoid glitches an propagate only stable results .the other advantage of pipe lined architecture is to reduce the critical path.
well am working on a low frequency project 30khz so delay is not an issue and the period of a clock is moooore than enough to perform all four operations .
the problem that latches or register are area and power consuming .
i would like to know if the it is a good choice to eliminate the registers between each block. and if am going to loose the power consumption i save from register on glitches