I have been watching Ben Eater's Building an 8-Bit Breadboard Computer.

Let's say that I use the following version of a positive edge-triggered program counter, taken from the book Digital Logic and Computer Design, by M. Morris Mano -

enter image description here

The following image shows the negative edge-triggered master-slave JK flip-flops used in the counter.

enter image description here

Initially, the Y outputs of all master gated latches and the Q outputs of all slave gated latches are 0's.

Now, let's say that control signals are generated via an EEPROM (i.e. the control unit is microprogrammed).

The control unit generates new signals when the master clock becomes 0 and the step counter counts up.

Now, the master clock (i.e. the CP input) becomes 0 and according to the current control word, the count input becomes 1 and the load input stays 0. This causes the Y output of the topmost flip-flop's master latch to become 1.

Now, the master clock becomes 1, which causes the Q output of the topmost flip-flop's slave latch to become 1.

Finally, when the master clock becomes 0 again, then according to the next control word, the count input becomes 0, ideally preventing the counter from counting anymore.

But, since the control words need time to get generated, wouldn't the Y output of the topmost flip-flop's master latch become 0 while the count input is still at 1 due to the previous control word?

Here is the timing diagram -

CP, Load and Count are inputs to the counter, and the outputs Y and Q are of the topmost flip-flop's master and slave gated latches.

enter image description here

  • 4
    \$\begingroup\$ You could double check this using a simulator very easily at no cost to you except a little time learning to use a very, very important tool. \$\endgroup\$
    – Andy aka
    Oct 11, 2023 at 17:50
  • 4
    \$\begingroup\$ That's a lot of words. Can you draw a timing diagram that illustrates the relationships you're talking about? Be clear about which node in the diagram is represented by each waveform. While you're at it, please rotate your image 90° so that we all don't need to strain our necks trying to read it. \$\endgroup\$
    – Dave Tweed
    Oct 11, 2023 at 18:37
  • \$\begingroup\$ @DaveTweed, I'm sorry. Will do once I reach home. \$\endgroup\$ Oct 11, 2023 at 18:43
  • \$\begingroup\$ @DaveTweed, I've edited my question. Could you please take a look at it now? \$\endgroup\$ Oct 12, 2023 at 11:09

1 Answer 1


OK, now I see what you're talking about. The problem is that your second diagram is not a correct diagram for a true edge-triggered J-K flip-flop. It's a diagram you'll find all over the Internet, because it kinda-sorta explains the general concept, but if you check any commercial datasheets for JKFFs (e.g., 74xx76), you'll find that their actual internal logic looks completely different.

So, if you accept that a true JKFF only changes its outputs based on the J and K inputs at the time of the active edge of the clock, then the larger binary counter circuit works as expected.

  • \$\begingroup\$ Would you please have a look at electronics.stackexchange.com/q/685232/347018? I'm having trouble understanding the working of the 74LS76A. \$\endgroup\$ Oct 15, 2023 at 4:35
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    \$\begingroup\$ Yes, I've seen it. The standard 6-gate diagram for the DFF is similarly mind-bending. The design of asynchronous state machines definitely involves a degree of "black magic", and reverse-engineering them from the schematic requires some fairly deep insight. I'll spend some time on it if I get a chance. \$\endgroup\$
    – Dave Tweed
    Oct 15, 2023 at 12:09

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