I'm currently redesigning a breakout board for an expensive FPGA data acquisition device we work with frequently. The designer of the past version added some components between the FPGA's digital IO (DIO) ports and the breakout outputs which I believe are meant to protect the FPGA from whatever is downstream. Downstream electronics usually involve voltages from 0V to 5V, but sometimes -15V to 30V, so I presume they wanted to protect against accidental over- or under-voltage.

I'm trying to understand the design choices, and it doesn't make sense to me. Here is the breakout board circuit for each of the many DIO channels:

Ground connected to TBAT54S_LM pin 1, +5V connected to TBAT54S_LM pin 3, DIO and thermistor pin 1 connected to TBAT54S_LM pin 2, thermistor pin 2 connected to DIO breakout

Here are the specs for the DIO lines:

Max tested current per channel...............±3 mA

Input logic levels

  • Input low voltage, VIL ......................0 V min; 0.8 V max
  • Input high voltage, VIH ....................2.0 V min; 5.25 V max

Output logic levels

  • Output high voltage, VOH sourcing 3 mA .................................2.4 V min; 3.465 V max
  • Output low voltage, VOL sinking 3 mA ...................................0.0 V min; 0.4 V max

The thermistor makes sense to me - the DIO lines should not be sinking or sourcing more than a few mA of current, so if they do, the thermistor heats up and quickly cuts off the current, protecting the input.

The pair of Schottke diodes (the TBAT54S IC) makes less sense to me. As best I can tell, the idea is to clamp the input between 0 V and 5 V by providing a reverse path through a diode to either ground or 5V if the input voltage swings too far below 0V or above 5V. However, looking at the TBAT54S datasheet (see the graph below), it looks like even at 30V of reverse voltage, each diode will only allow ~500 nA of current backwards through the diode. So if whatever is accidentally over-voltaging the input can source significantly more than that, the diode isn't going to provide any useful protection, right?

Wouldn't a pair of Zener diodes with Vz=5V make more sense, since they have the non-destructive avalanche breakdown regime that can sink a lot of current? I'd appreciate any help anyone can give me to either explain the logic behind the original circuit design, or confirm that it doesn't make sense. Thanks!

Ir - Vr curve for

  • 4
    \$\begingroup\$ The protection the diodes provide is when they are forward biased. Only between 0V and 5V are both diodes reverse biased and are intentionally not affecting the signal. Outside of that range, one diode becomes forward biased and clamps the voltage to the respective limit. \$\endgroup\$
    – user107063
    Oct 12, 2023 at 1:33
  • \$\begingroup\$ @user107063 Transfer that to an answer. \$\endgroup\$
    – MiNiMe
    Oct 12, 2023 at 2:10
  • \$\begingroup\$ Oh, right, that...makes sense. For some reason I was focusing on the reverse current. I guess if the input tries to go higher than 5V then the 5V pin will sink the current, and if it goes lower than ground, the ground pin will source current to bring the pin back to ground. Is that correct? \$\endgroup\$
    – Brionius
    Oct 12, 2023 at 12:57

1 Answer 1


Note that reverse bias more than about 6V is never experienced by either diode; see their orientation with respect to the supplies.

Zeners aren't required if the supply can sink the injected current instead.

Also in case of using zeners, a single 5V zener could be used, since it will forward conduct from GND, or break down at about 5V, and no reference to +5V supply is needed at all, at least by itself. (Note that I'm specifically not generalizing this sentence. Zeners under 6V are increasingly "soft" -- a common cause of confusion, say when a newbie tries to clamp a 5V logic signal to 3V but then it only develops 2.3V or something, because the 3.0 or 3.3V zener diode used, requires so much current to actually develop the rated voltage drop. Higher voltages are perfectly workable of course, but it's less common we are using logic above 5V, and extremely rare indeed above 15V.)

Note that the device being protected, may have internal supply clamping diodes (i.e. diode from pin to VDD), which a zener would not protect (when the circuit is unpowered).

It's noteworthy that BAT54S isn't rated for ESD, at least in any datasheets I've looked at. Schottky diodes are generally poor performers in surge conditions; they have higher capacitance and internal resistance than equal sized PN diodes, so the lower voltage drop (at modest current levels) is traded to some extent with signal bandwidth and peak clamping ability, or with fusing ratings (another surge condition) in the case of rectifiers. For this reason, they are usually designed with a PN "guard ring", which serves several practical purposes, but one of them is to sink surge currents (both in forward and reverse/avalanche conditions).

Probably, it would be technically better (or strictly, even, at least as far as ESD is concerned) to use PN diodes in the first place, i.e. do what the guard ring is providing and skip the schottky part altogether. That said, I've used BAT54S many times, and haven't experienced any failures in IEC 61000-4-2 8/15kV level ESD testing. PN diodes are widely available, from BAV99 and friends, to combo TVS arrays like CDSOT23-SRV05-4.

Anyway, whether such inputs are suitable for cross-wiring to higher voltages, isn't clear. The PRF18BB471QB5RB is a PTC type thermistor; in an 0603 chip package, it won't take much energy to "open" up, but it will take some time (PTC fuses typically open in 10s to 100s of ms), especially at the 470Ω nominal rating. If nothing else, if the system can withstand the continuous current through 470Ω, it can certainly handle it momentarily. For a 30V input, that's a 25V drop to the +5V supply, or 53mA. For a single pin being pulled high in this way, if the VDD load is more than 53mA already, this merely offsets load current; if not, then the supply will get pulled up until something else starts taking the current -- which may include breakdown of more precious components. And so on, if multiple pins might be pulled up at once.

Typically, a zener type TVS on the supply is sufficient to sink such currents. Parts rated for 6-8V (abs. max) typically break down at 9-12V, so using a 5V TVS like SMAJ5.0A is effective protection. Of course, one might not want to rely on such an assumption (or the supply voltage is used for other purposes like a reference, so should be constrained tighter), in which case a more accurate shunt can be used, like a "boosted" TLV431 shunt regulator circuit*, set moderately above the nominal-max supply voltage (so as to avoid accidentally sinking the power supply's normal output!). A crowbar can also be used, if one doesn't mind the whole thing shutting down as a consequence.

*Note that TLV431, while commonly sold as an "adjustable zener", is in fact a control circuit, a peculiar op-amp with a ponderously large yet curiously stable input offset voltage. This is worth reflecting on, because it means it cannot respond instantaneously, but must take some time to respond, to within some regulation margin. For shorter time periods (some ~µs), supply bypass capacitors must handle the job, passively, instead. From this, we can calculate the minimum total supply capacitance required, to handle a given input surge. Most likely, this capacitance is already present in circuit, and no change is necessary, but it is good to be aware of these facts.

A clamping rail can also be used, with its own zener diode, and it can either be biased up by input pins themselves, or if less capacitance / transient weirdness is desired, it can be biased from a resistor from VDD, the resistor thus limiting backfeeding into VDD itself. That is, instead of clamping to VDD, clamp to a new rail, with bypass capacitors strewn about and all that, but separate from VDD so as not to disturb it.

Finally, it's not clear if this is any problem at all, but noting for posterity: note that these digital inputs will not be especially high bandwidth, given the 10s of pF capacitance loading them, and the 470Ω series resistor. If this is a general purpose desktop sort of DAQ thing, that probably doesn't matter, but do note it precludes its use as a high-bandwidth logic analyzer or something like that, for instance. A smaller value resistor could be used to address this (which could still be a PTC type for limiting, given a clamping method of higher capacity), or other means like a depletion MOS current limiter.


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